Device for accessing registered circuit units
View Patent ↗A device is provided for accessing circuit units via access registers. The circuit units have a plurality of inputs for access to said circuit units. A first access register having register outputs which are connected to a first part of the inputs of at least one first circuit unit, and having register outputs which are connected to inputs of at least one second circuit unit is provided. In addition, a second access register having register outputs which are connected to a second part of the inputs of said at least one first circuit unit, and having register outputs connected to inputs of at least one third circuit unit is provided. Moreover, an access register is provided which has a number of register inputs, first register outputs for driving the inputs of at least one first circuit unit, each register input having associated therewith a first register output, and second register outputs for driving part of the inputs of at least one second circuit unit, a subset of the register inputs having associated therewith a second register output.
1. A device for accessing circuit units via access registers, the circuit units comprising a plurality of inputs for access to said circuit units, said device comprising:
a first access register having register outputs which are connected to a first part of the inputs of at least one first circuit unit, and having register outputs which are connected to inputs of at least one second circuit unit; and
a second access register having register outputs which are connected to a second part of the inputs of said at least one first circuit unit, and having register outputs connected to inputs of at least one third circuit unit.
2. The device according to claim 1 , wherein the first access register, the second access register or both have register inputs, the register outputs connected to the at least one first circuit unit being lower in number than the register inputs.
3. The device according to claim 2 , wherein each register output has associated therewith a register input.
4. The device according to claim 1 , wherein said at least one first circuit unit, whose inputs have connected thereto outputs of said first and second access registers, is arranged spatially between said first and second access registers.
5. The device according to claim 1 , wherein the access registers have n register inputs and wherein the number of the first and second parts of the inputs of the at least one first circuit unit is n/2 respectively.
6. The device according to claim 1 , wherein the circuit units are memory chips and wherein the access registers are memory registers.
7. The device according to the claims 1 for accessing a plurality of circuit units, wherein the circuit units are arranged substantially symmetrically with respect to the access registers.
8. The device according to claim 7 , wherein the circuit units are arranged relative to the access registers in such a way that the second and third circuit units are spatially associated with a respective access register, and said at least one first circuit unit is spatially associated with two access registers, the inputs of the at least one first circuit unit being connected to register outputs of the two spatially associated access registers.
9. The device according to claim 8 , wherein the at least one first circuit unit is arranged between the spatially associated access registers.
10. The device according to claim 1 for driving a plurality of circuit units, wherein each register output is connected to the same number of inputs of circuit units.
11. An access register comprising:
a number of register inputs;
first register outputs for driving the inputs of at least one first circuit unit, each register input having associated therewith a first register output; and
second register outputs for driving part of the inputs of at least one second circuit unit, and only a subset of the register inputs having associated therewith a second register output.