Patent Assignment
Reel/Frame 036818/0583
Assignment of Assignor's Interest
Recorded: 2015-10-08
Received: 2015-10-08
Pages: 14
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IEX, IRELAND
Covered Properties
(100)
System and Method for Testing One or More Dies on a Semiconductor Wafer
Application:
11/707,408 →
Continuous Self-Calibration of Internal Analog Signals
Application:
11/649,047 →
System and Method for Testing One or More Dies on a Semiconductor Wafer
Application:
11/386,512 →
Capacitorless 1-Transistor Dram Cell and Fabrication Method
Application:
11/367,731 →
Vertically Integrated Field-Effect Transistor Having a Nanostructure Therein
Application:
10/533,550 →
Method and Device for Packaging and Transporting Electronic Components
Application:
10/507,935 →
Method for Masking a Recess in a Structure Having a High Aspect Ratio
Application:
10/501,464 →
Trench Capacitor with Buried Strap
Application:
11/053,508 →
Method of Producing a Layered Arrangement and Layered Arrangement
Application:
10/498,421 →
Method for on-die detection of the system operation frequency in a DRAM to adjust DRAM operations
Application:
11/042,624 →
Method for Determining the Construction of a Mask for the Micropatterning of Semiconductor Substrates by Means of Photolithography
Application:
11/029,573 →
Electronic Component and Panel and Method for Producing the Same
Application:
10/501,599 →
Method and Apparatus for Homogeneously Magnetizing an Exchange-Coupled Layer System of a Digital Magnetic Memory Cell Device
Application:
10/495,301 →
High Density Dram with Reduced Peripheral Device Area and Method of Manufacture
Application:
11/003,592 →
Method of Producing an Electronic Component and a Panel with a Plurality of Electronic Components
Application:
10/989,650 →
Silicon Particles as Additives for Improving Charge Carrier Mobility in Organic Semiconductors
Application:
10/974,774 →
Electronic Component Having at Least One Semiconductor Chip and Flip-Chip Contacts, and Method for Producing the Same
Application:
10/960,994 →
Maskless Middle-of-Line Liner Deposition
Application:
10/960,735 →
System and Method for Enabling a Vendor Mode on an Integrated Circuit
Application:
10/940,382 →
Floating Gate Memory Cell with a Metallic Source/Drain and Gate, and Method for Manufacturing Such a Floating Gate Memory Gate Cell
Application:
10/926,838 →
Process for Producing a Plurality of Gate Stacks Which Are Approximately the Same Height and Equidistant on a Semiconductor Substrate
Application:
10/916,742 →
Capacitorless 1-Transistor Dram Cell and Fabrication Method
Application:
10/911,994 →
Method for Producing an Electrically Conductive Contact
Application:
10/893,561 →
Method for Producing a Protection for Chip Edges and System for the Protection of Chip Edges
Application:
10/890,827 →
Electronic Component and Method for Its Production
Application:
10/868,855 →
Probe Needle for Testing Semiconductor Chips and Method for Producing Said Probe Needle
Application:
10/826,954 →
Method of Forming an Alignment Mark Structure Using Standard Process Steps for Forming Vertical Gate Transistors
Application:
10/762,973 →
Method for Fabricating a Photomask for an Integrated Circuit and Corresponding Photomask
Application:
10/736,775 →
Simulated Module Load
Application:
10/654,342 →
Semiconductor Circuit Module and Method for Fabricating Semiconductor Circuit Modules
Application:
10/630,632 →
System of Multiplexed Data Lines in a Dynamic Random Access Memory
Application:
10/623,078 →
Vertical Transistor, and a Method for Producing a Vertical Transistor
Application:
10/615,567 →
Memory Chip with Test Logic Taking into Consideration the Address of a Redundant Word Line and Method for Testing a Memory Chip
Application:
10/610,186 →
Method for Storing Data, Method for Reading Data, Apparatus for Storing Data and Apparatus for Reading Data
Application:
10/602,403 →
Method for Increasing the Input Voltage of an Integrated Circuit with a Two-Stage Charge Pump, and Integrated Circuit
Application:
10/600,961 →
Method for Structuring a Lithography Mask
Application:
10/465,103 →
Method for Structuring a Silicon Layer
Application:
10/463,565 →
Integrated Circuit with Voltage Divider and Buffered Capacitor
Application:
10/460,714 →
Method for Eliminating Phase Conflict Centers in Alternating Phase Masks, and Method for Producing Alternating Phase Masks
Application:
10/455,764 →
Memory Module with Test Structure
Application:
10/452,482 →
Vertical 8F2 Cell Dram with Active Area Self-Aligned to Bit Line
Application:
10/447,065 →
Memory Circuit, Method for Manufacturing and Method for Operating the Same
Application:
10/431,422 →
Method and Auxiliary Device for Testing a Ram Memory Circuit
Application:
10/429,579 →
Method of Increasing an Internal Operating Voltage for an Integrated Circuit, and Integrated Circuit
Application:
10/429,577 →
Signal Generator for Charge Pump in an Integrated Circuit
Application:
10/426,011 →
Process for Producing Hard Masks
Application:
10/425,233 →
Surface-Functionalized Inorganic Semiconductor Particles as Electrical Semiconductors for Microelectronics Applications
Application:
10/425,460 →
Ram Memory Circuit and Method for Controlling the Same
Application:
10/425,280 →
Method for Numerically Simulating an Electrical Circuit
Application:
10/422,580 →
Semiconductor Circuit and Initialization Method
Application:
10/419,596 →
Magnetic Memory
Application:
10/249,532 →
Low Switching Field Magnetic Element
Application:
10/249,531 →
Circuit Configuration with Signal Lines for Serially Transmitting a Plurality of Bit Groups
Application:
10/414,836 →
Targeted Deposition of Nanotubes
Application:
10/413,505 →
Drive Circuit and Control Method
Application:
10/410,933 →
Circuit Configuration for Converting Logic Signal Levels
Application:
10/410,383 →
Integrated Memory Having a Memory Cell Array Containing a Plurality of Memory Banks, and Circuit Configuration Having an Integrated Memory
Application:
10/409,012 →
Method for Compensating for Scatter/Reflection Effects in Particle Beam Lithography
Application:
10/408,806 →
Electrical Component with a Contact and Method for Forming a Contact on a Semiconductor Material
Application:
10/401,187 →
Electronic Component with a Semiconductor Chip, Method of Producing an Electronic Component and a Panel with a Plurality of Electronic Components
Application:
10/396,841 →
Semiconductor Memory Cell and Semiconductor Memory Device
Application:
10/395,428 →
Semiconductor Memory Cell and Semiconductor Memory Device
Application:
10/395,457 →
Method for Producing a Horizontal Insulation Layer on a Conductive Material in a Trench
Application:
10/394,932 →
Duty-Cycle Correction Circuit
Application:
10/393,525 →
Integrated Circuit and Method for Controlling a Power Supply Thereof
Application:
10/389,782 →
Method and Arrangement for Generating Ultrapure Steam
Application:
10/389,558 →
Test Method and Test Apparatus for an Electronic Module
Application:
10/389,580 →
Latency Time Circuit for an S-Dram
Application:
10/249,029 →
Limiter for Refresh Signal Period in Dram
Application:
10/386,150 →
Differental Current Source for Generating Dram Refresh Signal
Application:
10/386,147 →
Method for Producing a Shallow Trench Isolation for N- and P- Channel Field-Effect Transistors in a Semiconductor Module
Application:
10/385,000 →
Nonvolatile Memory Cell
Application:
10/248,985 →
Method for Filling Depressions on a Semiconductor Wafer
Application:
10/378,244 →
Resist for Electron Beam Lithography and a Process for Producing Photomasks Using Electron Beam Lithography
Application:
10/376,904 →
Adapter Apparatus for Memory Modules
Application:
10/377,349 →
Polymer Material Having a Low Glass Transition Temperature for Use in Chemically Amplified Photoresists for Semiconductor Production
Application:
10/377,893 →
Method and Magazine Device for Testing Semiconductor Devices
Application:
10/377,348 →
Process for Increasing the Etch Resistance and for Reducing the Hole and Trench Width of a Photoresist Structure Using Solvent Systems of Low Polarity
Application:
10/375,532 →
Method and Device for Depositing Thin Layers via Ald/Cvd Processes in Combination with Rapid Thermal Processes
Application:
10/375,529 →
Lithographic Process for Reducing the Lateral Chromium Structure Loss in Photomask Production Using Chemically Amplified Resists
Application:
10/375,531 →
Apparatus and Method for Monitoring a State, in Particular of a Fuse
Application:
10/374,916 →
Control Circuit for an S-Dram
Application:
10/248,874 →
Latency Time Switch for an S-Dram
Application:
10/374,657 →
Ferroelectric Memory Integrated Circuit with Improved Reliability
Application:
10/248,861 →
Method for Fabricating a P-Channel Field-Effect Transistor on a Semiconductor Substrate
Application:
10/372,989 →
Trench Capacitor with Buried Strap
Application:
10/248,801 →
Method for Forming a Hard Mask in a Layer on a Planar Device
Application:
10/370,857 →
Method for Generating Test Signals for an Integrated Circuit and Test Logic Unit
Application:
10/368,330 →
Integrated Dynamic Memory with Control Circuit for Controlling a Refresh Mode of Memory Cells, and Method for Driving the Memory
Application:
10/368,333 →
Process for the Plasma Etching of Materials Not Containing Silicon
Application:
10/356,106 →
Fluorine-Containing Photoresist Having Reactive Anchors for Chemical Amplification and Improved Copolymerization Properties
Application:
10/356,791 →
Resist for Photolithography Having Reactive Groups for Subsequent Modification of the Resist Structures
Application:
10/356,775 →
Chemical Mechanical Polishing (Cmp) Process Using Fixed Abrasive Pads
Application:
10/353,733 →
Magnetoresistive Memory Cell with Polarity-Dependent Resistance
Application:
10/352,730 →
Ddr Memory and Storage Method
Application:
10/350,482 →
Method of Resolving Missing Graphical Symbols in Computer-Aided Integrated Circuit Design
Application:
10/348,928 →
Method of Resolving Mismatched Graphical Symbols in Computer-Aided Integrated Circuit Design
Application:
10/348,847 →
Method of Resolving Mismatched Parameters in Computer-Aided Integrated Circuit Design
Application:
10/349,342 →
Apparatus for Connecting Semiconductor Modules
Application:
10/345,057 →
Digital Memory Circuit Having a Plurality of Memory Banks
Application:
10/342,901 →