Semiconductor memory cell and semiconductor memory device

1. A semiconductor memory cell including a field-effect transistor device based on organic semiconductor material, the field-effect transistor device comprising:

a first source/drain region, a second source/drain region, a channel region formed between said first source/drain region and said second source/drain region, a gate region having a gate electrode configuration with a first gate electrode, and an insulation region insulating said gate region from said channel region, said channel region having or being formed from an organic semiconductor material; and

at least one modulation region configured between said first gate electrode of said gate electrode configuration and said insulation region;

different information states being detectable and/or representable as different electric currents flowing through said channel region when a given electrical potential difference is applied between said first source/drain region and said second source/drain region;

said modulation region including modulation material having at least two states;

said modulation region being controllably modulatable between said states to electromagnetically influence said channel region, in accordance with said states, for a given electrical potential difference applied between said first gate electrode and said first and second source/drain regions; and

said modulation material of said modulation region enabling a capacitance modulation, said modulation material having a modulatable property selected from a group consisting of a specific electrical conductivity, a dielectric property, and a polarization property.

2. The semiconductor memory cell according to claim 1 , wherein said channel region has an electrical conductivity that is controllable by said states of said modulation material and/or by changes of said states of said modulation material.

3. The semiconductor memory cell according to claim 1 , wherein different electric field strengths and/or electrical potential differences are applied to said channel region by said states of said modulation material and/or by changes of said states of said modulation material.

4. The semiconductor memory cell according to claim 1 , wherein said modulation material has a property that can be modulated by a thermal exposure, electrical exposure, magnetic exposure, and/or electromagnetic exposure.

5. The semiconductor memory cell according to claim 1 , further comprising a second gate electrode.

6. The semiconductor memory cell according to claim 5 , wherein said second gate electrode is configured between said insulation region and said modulation region or between said insulation region and said modulation material.

7. The semiconductor memory cell according to claim 5 , wherein said second gate electrode is configured directly adjacent said insulation region.

8. The semiconductor memory cell according to claim 5 , wherein said modulation material is configured directly or immediately between said first gate electrode and said second gate electrode.

9. The semiconductor memory cell according to claim 5 , wherein said modulation region is configured directly or immediately between said first gate electrode and said second gate electrode.

10. The semiconductor memory cell according to claim 5 , wherein said second gate electrode is formed as a free gate electrode or as a floating gate.

11. The semiconductor memory cell according to claim 5 , further comprising a third gate electrode configured as a control electrode located directly laterally proximal to said second gate electrode.

12. The semiconductor memory cell according to claim 11 , further comprising an electrically insulating gate dielectric region configured between said third gate electrode and said insulation region.

13. The semiconductor memory cell according to claim 5 , further comprising an electrically insulating gate dielectric region configured between said second gate electrode and said insulation region.

14. The semiconductor memory cell according to claim 1 , wherein said modulation region has a first high-impedance state and a second low-impedance state.

15. The semiconductor memory cell according to claim 1 , wherein said modulation material has a first high-impedance state and a second low-impedance state.

16. The semiconductor memory cell according to claim 1 , wherein said modulation material includes an organic compound and/or an inorganic compound.

17. The semiconductor memory cell according to claim 1 , wherein said modulation material is formed as a monolayer of an organic compound and/or an inorganic compound.

18. The semiconductor memory cell according to claim 1 , wherein said modulation material includes an organic compound based on a material selected from a group consisting of bispyridinium, TCNQ, an organometallic compound of bispyridinium, and an organometallic compound of TCNQ.

19. The semiconductor memory cell according to claim 1 , wherein said modulation material includes Cu/TCNQ.

20. The semiconductor memory cell according to claim 1 , wherein said modulation material includes inorganic modulation material selected from a group consisting of chalcogenides and solid-state ionic conductors including a metal.

21. The semiconductor memory cell according to claim 1 , further comprising a gate dielectric including an inorganic compound and/or an organic compound.

22. The semiconductor memory cell according to claim 1 , further comprising a gate dielectric formed from an inorganic compound and/or an organic compound.

23. The semiconductor memory cell according to claim 1 , further comprising a gate dielectric including an organic material selected from a group consisting of polymers, polystyrene, polyethylene, polyester, polyurethane, polycarbonate, polyacrylate, polyimide, polyether, polybenzoxazoles, mixtures thereof, and compounds thereof.

24. The semiconductor memory cell according to claim 1 , further comprising a gate dielectric including an inorganic material selected from a group consisting of silicon dioxide, silicon nitride, aluminum oxide, zinc oxide, hafnium oxide, mixtures thereof, and compounds thereof.

25. The semiconductor memory cell according to claim 1 , wherein at least one element selected from a group consisting of said first source/drain region, said second source/drain region, and said first gate electrode includes or is formed from a metal.

26. The semiconductor memory cell according to claim 25 , wherein said metal is selected from a group consisting of palladium, gold, platinum, nickel, copper, titanium, mixtures thereof, and compounds thereof.

27. The semiconductor memory cell according to claim 1 , comprising at least one lead including a metal selected from a group consisting of palladium, gold, platinum, nickel, copper, titanium, mixtures thereof, and compounds thereof.

28. The semiconductor memory cell according to claim 1 , wherein at least one element selected from a group consisting of said first source/drain region, said second source/drain region, and said first gate electrode includes or is formed from a doped semiconductor material.

29. The semiconductor memory cell according to claim 28 , wherein said doped semiconductor material includes an inorganic and/or organic semiconductor material selected from a group consisting of camphorsulfonic-acid-doped polyanilines, polystyrenesulfonic-acid-doped polythiophenes, mixtures thereof, and compounds thereof.

30. The semiconductor memory cell according to claim 1 , comprising at least one lead including a doped inorganic and/or organic semiconductor material.

31. The semiconductor memory cell according to claim 30 , wherein said doped semiconductor material is selected from a group consisting of camphorsulfonic-acid-doped polyanilines, polystyrenesulfonic-acid-doped polythiophenes, mixtures thereof, and compounds thereof.

32. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is a p-type semiconductor material.

33. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on a condensed aromatic compound.

34. The semiconductor memory cell according to claim 33 , wherein said condensed aromatic compound is selected from a group consisting of anthracene, tetracene, and pentacene.

35. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on polythiophene.

36. The semiconductor memory cell according to claim 35 , wherein said polythiophene is selected from a group consisting of poly-3-alkylthiophene and polyvinylthiophene.

37. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on an organometallic complex.

38. The semiconductor memory cell according to claim 37 , wherein said organometallic complex uses a copper of phthalocyanine or porphyrin.

39. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is a p-type semiconductor material.

40. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on a condensed aromatic compound.

41. The semiconductor memory cell according to claim 40 , wherein said condensed aromatic compound is selected from a group consisting of anthracene, tetracene, and pentacene.

42. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on polythiophene.

43. The semiconductor memory cell according to claim 42 , wherein said polythiophene is selected from a group consisting of poly-3-alkylthiophene and polyvinylthiophene.

44. The semiconductor memory cell according to claim 1 , wherein said organic semiconductor material is based on an organometallic complex.

45. The semiconductor memory cell according to claim 44 , wherein said organometallic complex uses a copper of phthalocyanine or porphyrin.

46. The semiconductor memory cell according to claim 1 , further comprising a flexible substrate.

47. The semiconductor memory cell according to claim 46 , wherein said flexible substrate includes at least one metal selected from a group consisting of nickel, gold, and iron sheet.

48. The semiconductor memory cell according to claim 46 , wherein said flexible substrate includes at least one plastic selected from a group consisting of polystyrene, polyethylene, polyester, polyurethane, polycarbonate, polyacrylate, polyimide, polyether, and polybenzoxazole.

49. The semiconductor memory cell according to claim 46 , wherein said flexible substrate includes paper.

50. A semiconductor memory device including a plurality of memory cells, each one of the plurality of memory cells including a field-effect transistor device based on organic semiconductor material, the field-effect transistor device comprising:

a first source/drain region, a second source/drain region, a channel region formed between said first source/drain region and said second source/drain region, a gate region having a gate electrode configuration with a first gate electrode, and an insulation region insulating said gate region from said channel region, said channel region having or being formed from an organic semiconductor material; and

at least one modulation region configured between said first gate electrode of said gate electrode configuration and said insulation region;

different information states being detectable and/or representable as different electric currents flowing through said channel region when a given electrical potential difference is applied between said first source/drain region and said second source/drain region;

said modulation region including modulation material having at least two states;

said modulation region being controllably modulatable between said states to electromagnetically influence said channel region, in accordance with said states, for a given electrical potential difference applied between said first gate electrode and said first and second source/drain regions; and

said modulation material of said modulation region enabling a capacitance modulation, said modulation material having a modulatable property selected from a group consisting of a specific electrical conductivity, a dielectric property, and a polarization property.

51. The semiconductor memory device according to claim 50 , wherein said first source/drain region of one of said plurality of said memory cells is connected to said first source/drain region of other ones of said plurality of said memory cells.

52. The semiconductor memory device according to claim 50 , wherein said second source/drain region of one of said plurality of said memory cells is connected to said second source/drain region of other ones of said plurality of said memory cells.

53. The semiconductor memory device according to claim 50 , wherein said gate region of one of said plurality of said memory cells is connected to said gate region of other ones of said plurality of said memory cells.

54. The semiconductor memory device according to claim 50 , comprising an additional metallization or metal track connecting said first source/drain region of one of said plurality of said memory cells to said first source/drain region of other ones of said plurality of said memory cells.

55. The semiconductor memory device according to claim 50 , comprising an additional metallization or metal track connecting said second source/drain region of one of said plurality of said memory cells to said second source/drain region of other ones of said plurality of said memory cells.

56. The semiconductor memory device according to claim 50 , comprising an additional metallization or metal track connecting said gate region of one of said plurality of said memory cells to said gate region of other ones of said plurality of said memory cells.