Vertically integrated field-effect transistor having a nanostructure therein

1. A vertically integrated field-effect transistor comprising:

a first electrically conductive layer;

a middle layer, formed partially from dielectric material, on the first electrically conductive layer;

a second electrically conductive layer on the middle layer; and

a nanostructure grown up in a via hole from the bottom of the via hole introduced into the middle layer such that the grown nanostructure does not contact adjacent sidewalls of the via hole, the nanostructure further comprising a first end portion that is coupled to the first electrically conductive layer and a second end portion that is coupled to the second electrically conductive layer;

wherein the first end portion of the nanostructure forms a first source/drain region and the second end portion of the nanostructure forms a second source/drain region of the field-effect transistor;

wherein the middle layer, between two adjacent dielectric sublayers, has a third electrically conductive layer, the thickness of which is less than the thickness of at least one of the dielectric sublayers;

wherein a thin ring structure formed by oxidizing the third electrically conductive layer resulting in an oxidized layer as the gate-insulating region of the field-effect transistor arranged in the third electrically conductive layer, which forms the gate electrode of the field-effect transistor, along the via hole that has been introduced therein.

2. The field-effect transistor of claim 1 , wherein catalyst material for catalyzing the formation of the nanostructure is arranged between the first conductive layer and the nanostructure.

3. The field-effect transistor of claim 2 , wherein the third electrically conductive layer surrounds the nanostructure in a region around the first or second end portion.

4. The field-effect transistor of claim 3 , wherein the thickness of the third electrically conductive layer is less than the thickness of both dielectric sub layers.

5. The field-effect transistor of claim 1 , wherein the middle layer has an additional electrically conductive layer, which at least one additional electrically conductive layer serves as an additional gate electrode of the field-effect transistor, with an additional ring structure formed from an electrically insulating material as an additional gate-insulating region of the field-effect transistor being arranged along the via hole that has been introduced in the additional electrically conductive layer.

6. The field-effect transistor of claim 1 , having an additional field-effect transistor above the field-effect transistor.

7. The field-effect transistor of claim 6 , wherein the field-effect transistor and the additional field-effect transistor are connected to one another as an inverter circuit.

8. The field-effect transistor of claim 1 , wherein the first and second electrically conductive layer includes one of a group comprising tantalum, tantalum nitride, titanium, molybdenum, aluminum, titanium nitride, and a ferromagnetic material.

9. The field-effect transistor of claims 5 , wherein the third and additional electrically conductive layer comprises one of a group comprising polysilicon, tantalum, titanium, niobium, and aluminum.

10. The field-effect transistor of claim 1 , wherein the dielectric material of the middle layer is one or a combination of the materials in a group comprising silicon dioxide, silicon nitride, and silicon dioxide doped with potassium ions.

11. The field-effect transistor of claim 1 , wherein the nanostructure includes one of a group comprising a nanotube, a bundle of nanotubes, and a nanorod.

12. The field-effect transistor of claim 11 , wherein the nanorod includes one of a group comprising silicon, germanium, indium phosphide, gallium nitride, gallium arsenide, zirconium oxide and a metal.

13. The field-effect transistor of claim 11 , wherein the nanotube is one of a group comprising a carbon nanotube, a carbon-boron nanotube, a carbon-nitrogen nanotube, a tungsten sulfide nanotube, and a chalcogenide nanotube.

14. The field-effect transistor of claim 2 , wherein the nanostructure is a carbon nanotube, and wherein the catalyst material is one of a group comprising iron, cobalt, and nickel.

15. The field-effect transistor of claim 2 , wherein the nanostructure is a gallium arsenide nanorod, and wherein the catalyst material includes gold.

16. The field-effect transistor of claim 1 , formed exclusively from dielectric material, metallic material and the material of the nanostructure.

17. The field-effect transistor of claim 1 , formed on a substrate made from polycrystalline or amorphous material.

18. A field-effect transistor comprising:

a first conductive layer;

a middle layer on the first conductive layer, the middle layer having a via hole therein, and having a third conductive layer between two adjacent dielectric sublayers, the third electrically conductive layer forming the gate electrode of the field-effect transistor;

a second conductive layer on the middle layer;

a nanostructure grown up in a via hole from the bottom of the via hole such that the grown nanostructure does not contact adjacent sidewalls of the via hole and having a first source/drain region of the field-effect transistor that is coupled to the first conductive layer and a second source/drain region of the field-effect transistor that is coupled to the second conductive layer, and

thin ring-shaped means within the third electrically conductive layer of the middle layer along the via hole formed by oxidizing the third electrically conductive layer, for providing a gate-insulating region of the field-effect transistor.

19. The field-effect transistor of claim 18 , wherein the thickness of the third conductive layer is less than the thickness of the dielectric sublayers.

20. A vertically integrated field-effect transistor comprising:

a first electrically conductive layer;

a middle layer, formed partially from dielectric material, on the first electrically conductive layer;

a second electrically conductive layer on the middle layer; and

a nanostructure grown up in a via hole from the bottom of the via hole introduced into the middle layer such that the grown nanostructure does not contact adjacent sidewalls of the via hole, the nanostructure further comprising a first end portion that is coupled to the first electrically conductive layer and a second end portion that is coupled to the second electrically conductive layer;

wherein the first end portion of the nanostructure forms a first source/drain region and the second end portion of the nanostructure forms a second source/drain region of the field-effect transistor;

wherein the middle layer, between two adjacent dielectric sublayers, has a third electrically conductive layer, the thickness of which is less than the thickness of at least one of the dielectric sublayers;

wherein a thin ring structure formed by oxidizing the third electrically conductive layer as gate-insulating region of the field-effect transistor is arranged in the third electrically conductive layer, which forms the gate electrode of the field-effect transistor, along the via hole that has been introduced therein,

wherein the middle layer has an additional electrically conductive layer, which at least one additional electrically conductive layer serves as an additional gate electrode of the field-effect transistor, with an additional ring structure formed from an electrically insulating material as an additional gate-insulating region of the field-effect transistor being arranged along the via hole that has been introduced in the additional electrically conductive layer.