IP Library Granted Patent US 7,074,696
Granted Patent B1
US 7,074,696 · App. 10/630,632 · Granted Jul 11, 2006

Semiconductor circuit module and method for fabricating semiconductor circuit modules

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Quick Facts
Patent No.
US 7,074,696
App. No.
10/630,632
Granted
Jul 11, 2006
Kind
B1
Abstract

The present invention provides a method for fabricating semiconductor circuit modules having the following steps: application of a patterned connection layer to a transfer substrate, application of active circuit devices and/or passive circuit devices with contact areas pointing toward the patterned connection layer, connection of the circuit devices to one another by means of a filler at least between the circuit devices, removal of the transfer substrate, and application of electrical connection devices for selective contact connection of the contact area of the circuit devices to one another.

Claims (24)

1. A method for fabricating a semiconductor circuit module, the method comprising:

providing circuit devices, each having a contact area on a front side thereof;

applying a patterned connection layer to a transfer substrate;

applying the front sides of the circuit devices to the patterned connection layer and arranging said circuit devices on said pattern connection layer, such that the contact areas of said devices are not located on said patterned connection layer;

curing the patterned connection layer after applying said circuit devices;

applying a filler between the circuit devices;

removing the transfer substrate; and

applying an electrical connection device on said patterned connection layer to connect the circuit devices after removing said transfer substrate.

2. The method according to claim 1 , further comprising

applying a protection layer at least partially covering the electrical connection device.

3. The method according to claim 2 , further comprising

providing a second electrical connection device in a region not covered by the protection layer.

4. The method according to claim 1 , wherein

applying the patterned connection layer comprises printing the patterned connection layer on the transfer substrate.

5. The method according to claim 1 , further comprising

providing an encapsulation layer on backsides of said circuit devices.

6. The method according to claim 5 , wherein

applying the encapsulation layer comprises selecting a process from the group consisting of casting and printing.

7. The method according to claim 5 , further comprising

curing said encapsulation layer before removing said transfer substrate.

8. The method according to claim 1 , wherein

applying the filler comprises selecting a process from the group consisting of casting and printing.

9. The method according to claim 1 , further comprising

curing said filler before removing said transfer substrate.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036818/0583 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023796/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2004
From: FRANKOWSKI, GERD; HEDLER, HARRY; VASQUEZ, BARBARA
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015012/0492 →