Memory circuit, method for manufacturing and method for operating the same

1. Memory circuit, comprising:

several voltage generators for generating an operating voltage for memory elements of the memory circuit;

mean for selectively setting a current being deliverable by the several voltage generators depending on an operating frequency for the memory circuit;

the means for selectively setting including means for selectively deactivating the voltage generators depending on the operating frequency; and

means for determining whether the operating frequency is lower than a predetermined boundary frequency;

the means for selectively deactivating being constructed to deactivate at least one of the voltage generators when the operating frequency is lower than the predetermined boundary frequency; and

the means for determining including means for determining whether a period of a clock signal applied to the memory circuit is longer than a boundary period corresponding to the predetermined boundary frequency.

2. Memory circuit according to claim 1 , wherein the means for determining whether the period is longer than the boundary period includes:

a first D flip flop having a clock input, a D input, a non-inverting output and an inverting output;

a second D flip flop having a clock input, a D input (D) and a non-inverting output;

a delay circuit having an input and an output for receiving an input signal at the input and for outputting an output signal at the output, wherein the output signal is delayed by a predetermined period of time corresponding to the boundary period in relation to the input signal; and

an AND gate with an inverting input, a first, a second and a third non-inverting input and an output.

wherein the clock input of the first D flip flop and the inverting input of the AND gate arm connected to a clock signal input of the memory circuit,

wherein the non-inverting output of the first D flip flop is connected to the input of the delay circuit and the first non-inverting input of the AND gate,

wherein the inverting output of the first D flip flop is connected to the D input of the first D flip flop.

wherein the output of the delay Circuit is connected to the second non-inverting input of the AND gate,

wherein an initialization signal input of the memory circuit is connected to the third non-inverting input of the AND gate and to the D input of the second flip flop,

wherein the output of the AND gate is connected to the clock

input of the second flip flop, and

wherein the non-inverting output of the second D flip flop connected to a deactivation signal output of the means for selectively deactivating.

3. Memory circuit according to claim 1 , further comprising a means for determining whether the operating frequency is lower than a further predetermined boundary frequency,

wherein the means for selectively deactivating is further provided to deactivate a further one of the voltage generators when the operating frequency is lower than the further predetermined boundary frequency.

4. Method for manufacturing a memory circuit, comprising:

providing a plurality of voltage generators;

determining whether an operating frequency of the memory circuit is lower than a predetermined boundary frequency; and

permanently deactivating least one of the plurality of voltage generators when the operating frequency is lower than the predetermined boundary frequency.

5. Method according to claim 4 , wherein the step of deactivating includes a step of masking or step of blowing a fuse.

6. Method for operating a memory circuit including a plurality of voltage generators, comprising:

determining whether an operating frequency of the memory circuit is lower than a predetermined boundary frequency by determining whether a period of a clock signal applied to the memory circuit is longer than a boundary period corresponding to the predetermined boundary frequency; and

deactivating at least one of the voltage generators when the operating frequency is lower than the boundary frequency.

7. Method according to claim 6 , wherein the steps of determining and of deactivating are performed during an initialization of a memory circuit.

8. Memory circuit, comprising:

one or several voltage generators for generating an operating voltage for memory elements of the memory circuit; and

means for selectively setting a current deliverable by the one or the several voltage generator depending on an operating frequency for the memory circuit by permanently deactivating one of the voltage generators.

9. Memory circuit according to claim 8 , wherein the means for selectively setting includes a maskable programming means or a meltable fuse for programming the deliverable current.

10. Memory circuit, comprising:

several voltage generator for generating an operating voltage for memory elements of the memory circuit; and

means for selectively setting a current deliverable by the several voltage generators depending on an operating frequency for the memory circuit;

the means for selectively setting including means for turning off at least one of the voltage generators depending on the operating frequency.