Capacitorless 1-transistor DRAM cell and fabrication method
View Patent ↗The channel region ( 11 ) and the source-drain regions ( 9, 10 ) are arranged vertically at a sidewall of a dielectric trench filling ( 4 ). On the opposite side, the semiconductor material is bounded by the gate dielectric ( 18 ) and the gate electrode ( 16 ), which is arranged in a cutout of the semiconductor material. A memory cell array comprises a multiplicity of vertically oriented strip-type semiconductor regions in which source-drain regions are implanted at the top and bottom and a channel region embedded in insulating material on all sides is present in between as a floating body.
1. A capacitorless 1-transistor DRAM cell comprising:
doped source-drain regions disposed in semiconductor material;
a channel region disposed in the semiconductor material between doped source-drain regions, wherein the source-drain regions are embedded in a dielectric material in such a way that the channel region is at least partially depleted of charge carriers in the absence of an applied electrical potential; and
a gate electrode arranged alongside the channel region, the gate electrode being insulated from the channel region by a gate dielectric;
wherein:
a region made of the dielectric material is formed at a top side of a semiconductor body;
the channel region is arranged at a sidewall of the region made of the dielectric material;
the source-drain regions adjoin the channel region on both sides in the vertical direction with regard to the top side;
the gate electrode is arranged alongside of the channel region that is remote from the region made of the dielectric material and in a manner isolated from said channel region by the gate dielectric;
the gate electrode is electrically coupled to a word line; and
an upper one of the source-drain regions is electrically coupled to a bit line.
2. The DRAM cell as claimed in claim 1 , wherein the semiconductor material of the channel region is bounded by the dielectric material toward all sides in a sectional plane that is co-planar with respect to the top side.
3. The DRAM cell as claimed in claim 2 , wherein the semiconductor material of the channel region has dimensions which are smaller in the vicinity of the gate electrode than in the vicinity of the region made of the dielectric material in directions which run parallel to a boundary between the semiconductor material of the channel region and the region made of the dielectric material in a sectional plane that is co-planar with respect to the top side.
4. An arrangement comprising a plurality of 1-transistor DRAM cells as claimed in claim 1 , wherein:
a plurality of regions made of dielectric material that are arranged at a distance from one another are present at the top side of the semiconductor body;
between the regions made of dielectric material, the semiconductor material is in each case removed except for portions which are present at the sidewalls of the regions made of the dielectric material and are provided for channel regions and source-drain regions, so that a cutout is in each case present between said remaining portions of the semiconductor material; and
gate electrodes are arranged in said cutouts.
5. The arrangement as claimed in claim 4 , wherein:
electrically conductive layers are present at the top side above the regions made of the dielectric material; and
said electrically conductive layers in each case connect together two upper source-drain regions with regard to the semiconductor body which are present at mutually opposite sidewalls of the relevant region made of the dielectric material.
6. The arrangement as claimed in claim 4 , wherein a lower one of the source-drain regions with regard to the semiconductor body is formed as a continuous doped region in the manner of a ground plate.