IP Library Granted Patent US 6,950,995
Granted Patent B2
US 6,950,995 · App. 10/348,847 · Granted Sep 27, 2005

Method of resolving mismatched graphical symbols in computer-aided integrated circuit design

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Quick Facts
Patent No.
US 6,950,995
App. No.
10/348,847
Granted
Sep 27, 2005
Kind
B2
Abstract

A system and method for resolving mismatched graphical symbols in computer-aided design of integrated circuits during schematic migration. The system compares the dimensions of the graphical symbols within the circuit primitives of the target and source schematic databases and detects if the parameters are different. If so, the system alters the graphical symbols in the target circuit primitive to resolve the mismatch.

Claims (41)

1. A method of resolving mismatched graphical symbols in a computer-aided integrated circuit design system, the method comprising:

(a) reading a source dimension of a source graphical symbol from a source circuit primitive in a source schematic database, the source schematic database having a source schematic including source circuit primitives;

(b) reading a target dimension of a target graphical symbol from a target circuit primitive in a target schematic database, the target schematic database having a target schematic including source circuit primitives, wherein the target circuit primitive corresponds to the source circuit primitive;

(c) automatically comparing the source dimension with the target dimension; and

(d) altering the target graphical symbol in the target circuit primitive if the source dimension and the target dimension are not identical, to obtain an altered target graphical symbol, the target graphical symbol being altered along at least one target dimension such that there are no dangling lines when the altered target graphical symbol is inserted into a target schematic in the target schematic database.

2. The method of claim 1 , wherein the source dimension is selected from the group consisting of: width, height, and area.

3. The method of claim 1 , wherein the target dimension is selected from the group consisting of: width, height, and area.

4. The method of claim 1 , wherein (d) comprises:

replacing the target graphical symbol in the target circuit primitive with the source graphical symbol if the source dimension and the target dimension are not identical.

5. The method of claim 1 , wherein (d) comprises:

resizing the target graphical symbol so that the altered target graphical symbol has a resized target dimension equal to the source dimension; and

replacing the target graphical symbol in the target circuit primitive with the resized target graphical symbol.

6. The method of claim 5 , wherein the resized target dimension is selected from the group consisting of: width, height, and area.

7. The method of claim 1 , wherein (d) comprises:

substituting the target graphical symbol by a substitute target graphical symbol as the altered target graphical symbol, wherein the substitute target graphical symbol has as a substitute target dimension equal to the source dimension, and wherein a function of the substitute target graphical symbol is equal to a function of the target graphical symbol; and

replacing the target graphical symbol in the target circuit primitive with the substitute target graphical symbol.

8. The method of claim 7 , wherein the substitute target dimension is selected from the group consisting of: width, height, and area.

9. The method of claim 1 further comprising:

(e) renaming the target circuit primitive to obtain a name for a target circuit primitive having the altered target graphical symbol.

10. The method of claim 1 further comprising:

(e) creating a log file of actions performed during steps (a), (b), (c) and (d).

11. A computer readable medium, having stored therein instructions for causing a central processing unit to execute the steps of:

(a) reading a source dimension of a source graphical symbol from a source circuit primitive in a source schematic database, the source schematic database having a source schematic including source circuit primitives;

(b) reading a target dimension of a target graphical symbol from a target circuit primitive in a target schematic database, the target schematic database having a target schematic including source circuit primitives, wherein the target circuit primitive corresponds to the source circuit primitive;

(c) automatically comparing the source dimension with the target dimension; and

(d) altering the target graphical symbol in the target circuit primitive if the source dimension and the target dimension are not identical, to obtain an altered target graphical symbol, the target graphical symbol being altered along at least one target dimension such that there are no dangling lines when the altered target graphical symbol is inserted into a target schematic in the target schematic database.

12. A system for resolving mismatched graphical symbols in a computer-aided integrated circuit design system, comprising:

means for reading a source dimension of a source graphical symbol from a source circuit primitive in a source schematic database, the source schematic database having a source schematic including source circuit primitives;

means for reading a target dimension of a target graphical symbol from a target circuit primitive in a tarot schematic database, the target schematic database having a target schematic including source circuit primitives, wherein the target circuit primitive corresponds to the source circuit primitive;

means for automatically comparing the source dimension with the target dimension; and

means for altering the target graphical symbol in the target circuit primitive if the source dimension and the target dimension are not identical, to obtain an altered target graphical symbol, the target graphical symbol being altered along at least one target dimension such that there are no dangling lines when the altered target graphical symbol is inserted into a target schematic in the target schematic database.

13. A method of resolving mismatched graphical symbols in a computer-aided integrated circuit design system, the method comprising:

(a) reading a source dimension of a source graphical symbol from a source circuit primitive in a source schematic database;

(b) reading a target dimension of a target graphical symbol from a target circuit primitive in a target schematic database, wherein the target circuit primitive corresponds to the source circuit primitive;

(c) automatically comparing the source dimension with the target dimension; and

(d) altering the target graphical symbol in the target circuit primitive if the source dimension and the target dimension are not identical, by replacing the target graphical symbol in the target circuit primitive with the source graphical symbol.

14. A system for resolving mismatched graphical symbols in a computer-aided integrated circuit design system, comprising:

means for reading a source dimension of a source graphical symbol from a source circuit primitive in a source schematic database;

means for reading a target dimension of a target graphical symbol from a target circuit primitive in a tarot schematic database, wherein the target circuit primitive corresponds to the source circuit primitive;

means for automatically comparing the source dimension with the target dimension; and

means for altering the target graphical symbol in the target circuit primitive if the source dimension and the target dimension are not identical, wherein the means for altering is operative to replace the target graphical symbol in the target circuit primitive with the source graphical symbol.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 8, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036818/0583 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 14, 2003
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
To: INFINEON TECHNOLOGIES AG
Reel/Frame 013876/0553 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2003
From: HEGDE, SHAILESH U.; ISOM, MELVIN T., III
To: INFINEON TECHNOLOGIES NORTH AMERICA CORP.
Reel/Frame 013696/0047 →