High density DRAM with reduced peripheral device area and method of manufacture
View Patent ↗A dynamic random access memory (DRAM) structure having a distance less than 0.14 um between the contacts to silicon and the gate conductor is disclosed. In addition a method for forming the structure is disclosed, which includes forming the DRAM array contacts and the contacts to silicon simultaneously.
1. A method of forming a semiconductor structure having an array portion and a peripheral support portion, said method comprising:
providing a silicon substrate;
oxidizing the substrate to form a gate oxide layer;
depositing a gate conductor layer over the gate oxide layer;
depositing a gate cap insulator over the gate conductor layer;
etching at least one gate stack from the gate conductor and gate cap insulator, said gate stack having a top and sidewalls;
depositing a gate spacer layer and etching gate spacers along said sidewalls of the gate stack;
implanting at least one source and drain through said gate oxide layer into said substrate;
depositing a first dielectric layer on the silicon substrate;
depositing a second dielectric layer over the first dielectric layer;
forming at least one borderless array contact opening and at least one peripheral contact-to-diffusion opening simultaneously using a selective etching process, using a first etching mask;
forming at least one contact to the gate using an etching process nonselective to the gate cap and the gate spacers, using a second etching mask;
depositing a metallization mask over the second dielectric layer and patterning the metallization mask;
etching metallization lines into the second dielectric layer and stripping the metallization mask;
depositing a conductive layer over the metallization lines, said conductive layer filling said gate array contact, said peripheral contact-to-diffusion, and said gate contact; and
planarizing the conductive layer.
2. The method of claim 1 further comprising implanting transistor wells in the silicon substrate prior to oxidizing the substrate.
3. The method of claim 1 , wherein the semiconductor structure is a dynamic random access memory device.
4. The method of claim 1 , wherein the gate conductor comprises polysilicon and tungsten silicide.
5. The method of claim 1 , wherein the selective and nonselective etching processes are a reactive ion etch.
6. The method of claim 1 , wherein the conductive layer is selected from the group consisting of tungsten, aluminum, copper, aluminum-copper alloy, and tantalum.
7. The method of claim 1 , wherein the distance between the diffusion contacts and the gate conductor is less than about 0.075 μm.
8. The method of claim 1 , wherein the distance between the metallization lines is about 0.25 μm.
9. The method of claim 1 , wherein the first dielectric layer is selected from the group consisting of borophosphosilicate glass, phosphosilicate glass, FSG, F-BSG, or ASG.
10. The method of claim 1 , wherein said second dielectric layer is selected from the group consisting of TEOS, silicon dioxide, or borophosphosilicate glass.
11. The method of claim 1 , wherein the gate conductor is doped.
12. The method of claim 11 , wherein the doping is not uniform throughout the polysilicon.
13. The method of claim 1 , wherein the gate cap insulator and the spacers are formed from the same material.
14. The method of claim 13 , wherein the gate cap insulator and the spacers are silicon nitride.