Memory unit and branched command/address bus architecture between a memory register and a plurality of memory units
View Patent ↗A branched command/address bus architecture between a memory register and a plurality of memory units includes a main bus connected to the memory register. A first sub-bus is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same. A second sub-bus is also connected to the main bus and branches into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number. Further, the second sub-bus branches into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.
1. A branched command/address bus architecture between a memory register and a plurality of memory units, comprising:
a main bus connected to a memory register;
a first sub-bus which is connected to the main bus and branches into a first number of memory unit buses, wherein each of them is connected to a memory unit associated with a command/address input; and
a second sub-bus which is connected to the main bus and branches as follows:
into a second number of memory unit buses, wherein each of them is connected to a command/address input of a memory unit associated with the same, wherein the second number is smaller than the first number, and into a number of auxiliary buses, wherein the number of auxiliary buses corresponds to the difference between the first number and the second number, wherein each auxiliary bus is capacitively loaded corresponding to the memory unit buses and does not serve for driving a memory unit.
2. The branched command/address bus architecture according to claim 1 , wherein the capacitive load of the auxiliary bus is provided by an additional input of the memory unit comprising the same structure as the command/address input of this memory unit and being connected to the auxiliary bus.
3. The branched command/address bus architecture according to claim 1 , wherein each auxiliary bus is connected to a capacitor whose capacity corresponds to the input capacity of the command/address input of the memory units.
4. The branched command/address bus architecture according to claim 1 , wherein the memory units are DDR DRAM memory units.
5. The branched command/address bus architecture according to claim 3 , wherein the capacitor is a printed capacitor.
6. A memory unit, comprising:
a command/address input for receiving command/address signals via a memory unit bus from a memory register, wherein the command/address input comprises an input capacity; and
an additional auxiliary input, comprising the same input capacity as the command/address input, the additional auxiliary input being a dummy input not for signal transfer.
7. The memory unit according to claim 6 , wherein the additional auxiliary input comprises the same structure as the command/address input.