Semiconductor configuration and process for etching a layer of the semiconductor configuration using a silicon-containing etching mask
View Patent ↗To increase the etching resistance and to reduce the etching rate of a silicon-containing mask layer, an additional substance is mixed into the mask layer or into an etching gas. The additional substance is present in the mask layer or a concentration of the additional substance can be subsequently increased in the mask layer. During a subsequent etching process for patterning using the mask layer, the mask layer is removed at a reduced etching rate.
1. A semiconductor configuration, comprising:
a semiconductor substrate having a substrate surface;
a first layer configured on said substrate surface, said first layer including silicon oxide or silicon nitride and having a surface; and
a silicon-containing mask layer configured on said surface of said first layer;
said mask layer having an etching resistance and serving as an etching mask for said first layer;
said mask layer including a substance resulting in an increase of said etching resistance of said mask layer; and
said substance including a sulphur-hydrogen compound.
2. The semiconductor configuration according to claim 1 , wherein said substance forms a fraction of up to 50% of said mask layer.
3. The semiconductor configuration according to claim 1 , wherein said substance includes a concentration of more than 10 19 atoms per cm 3 of one of aluminium, gallium, indium, thallium.
4. The semiconductor configuration according to claim 1 , wherein said substance is implanted in said mask layer.
5. The semiconductor configuration according to claim 1 , wherein said substance is introduced into said mask layer by being supplied while said mask layer is being formed.
6. A process for etching a layer of a semiconductor configuration, the process which comprises:
forming a first layer including silicon oxide or silicon nitride on a substrate, the first layer having a surface;
forming a mask layer on the surface of the first layer, the mask layer including silicon;
patterning the mask layer for forming a mask pattern; and
etching the first layer using an etching gas containing sulphur-hydrogen compounds while using the etching mask to partially protect the surface of the first layer against the etching gas.
7. The process according to claim 6 , wherein during the etching step, sulphur-hydrogen compounds are increased in or on the mask layer.
8. The process according to one of claim 6 , wherein during the etching step, levels of sulphur atoms are increased in or on the mask layer.
9. A semiconductor configuration, comprising:
a semiconductor substrate having a substrate surface;
a first layer configured on said substrate surface, said first layer including silicon oxide or silicon nitride and having a surface; and
a silicon-containing mask layer configured on said surface of said first layer;
said mask layer having an etching resistance and serving as an etching mask for said first layer;
said mask layer including a substance resulting in an increase of said etching resistance of said mask layer; and
said substance including an implanted hydrocarbon chain.
10. A semiconductor configuration, comprising:
a semiconductor substrate having a substrate surface;
a first layer configured on said substrate surface, said first layer including silicon oxide or silicon nitride and having a surface; and
a silicon-containing mask layer configured on said surface of said first layer;
said mask layer having an etching resistance and serving as an etching mask for said first layer;
said mask layer including a substance resulting in an increase of said etching resistance of said mask layer; and
said substance including a concentration of more than 10 19 atoms per cm 3 of one of aluminium, gallium, indium, and thallium.