Patent Assignment
Reel/Frame 036575/0368
Assignment of Assignor's Interest
Recorded: 2015-09-09
Pages: 12
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(163)
Universal Resource Access Controller
Patent:
6,532,505 →
Application:
09/439,544 →
Uniform Recess Depth of Recessed Resist Layers in Trench Structure
Patent:
6,482,716 →
Application:
09/481,769 →
Method for Detecting and Classifying Scratches Occuring During Wafer Semiconductor Processing
Patent:
6,493,645 →
Application:
09/481,770 →
Techniques for Improving Memory Access in a Virtual Memory System
Patent:
6,442,666 →
Application:
09/491,408 →
Method for probing semiconductor devices for active measuring of electrical characteristics
Patent:
6,288,558 →
Application:
09/504,409 →
Dry process for cleaning residues/polymers after metal etch
Patent:
6,184,134 →
Application:
09/506,892 →
Address Decoding System and Method for Failure Toleration in a Memory Bank
Patent:
6,473,872 →
Application:
09/520,549 →
Method and apparatus for a flexible controller including an improved output arrangement for a dram generator system
Patent:
6,269,049 →
Application:
09/533,526 →
Method and Apparatus for an Essay Identification of a State of a Dram Generator Controller
Patent:
6,530,051 →
Application:
09/534,102 →
Method and apparatus for an improved reset and power-on arrangement for a dram generator controller
Patent:
6,141,284 →
Application:
09/534,103 →
Method and apparatus for a flexible controller for a dram generator system
Patent:
6,181,639 →
Application:
09/534,104 →
Dynamic Random Access Memory
Patent:
6,544,850 →
Application:
09/552,635 →
Control of Oxide Thickness in Vertical Transistor Structures
Patent:
6,372,567 →
Application:
09/553,708 →
Semiconductor Device Fabrication Using a Photomask Designed Using Modeling and Empirical Testing
Patent:
6,571,383 →
Application:
09/562,700 →
Metal Chemical Polishing Process for Minimizing Dishing During Semiconductor Wafer Fabrication
Patent:
6,943,113 →
Application:
09/569,220 →
Method of Forming a Vertically Oriented Device in an Integrated Circuit
Patent:
6,426,253 →
Application:
09/576,465 →
Generator scheme and circuit for overcoming resistive voltage drop on power supply circuits on chips
Patent:
6,310,511 →
Application:
09/595,696 →
Semiconductor Arrangement
Patent:
6,815,803 →
Application:
09/596,129 →
Semiconductor Package and Method
Patent:
6,730,989 →
Application:
09/596,130 →
Enhanced Overlay Measurement Marks for Overlay Alignment and Exposure Tool Condition Control
Patent:
6,727,989 →
Application:
09/597,123 →
Integrated circuit vertical trench device and method of forming thereof
Patent:
6,335,247 →
Application:
09/597,389 →
Elimination/Reduction of Black Silicon in Dt Etch
Patent:
6,489,249 →
Application:
09/597,441 →
Symmetric clock receiver for differential input signals
Patent:
6,294,940 →
Application:
09/598,349 →
DLL lock scheme with multiple phase detection
Patent:
6,388,482 →
Application:
09/598,350 →
Photomask and method for increasing image aspect ratio while relaxing mask fabrication requirements
Patent:
6,383,691 →
Application:
09/602,717 →
Method and System for Semiconductor Testing Using Yield Correlation Between Global and Class Parameters
Patent:
6,434,725 →
Application:
09/603,592 →
Method for High Speed Testing with Low Speed Semiconductor Test Equipment
Patent:
6,718,487 →
Application:
09/604,220 →
Strongly Water-Soluble Photoacid Generator Resist Compositions
Patent:
6,383,715 →
Application:
09/605,571 →
Automated bad socket masking in real-time for test handlers
Patent:
6,400,134 →
Application:
09/619,075 →
Method for Fabricating a Microtechnical Structure
Patent:
6,413,886 →
Application:
09/636,522 →
Wiring through terminal via fuse
Patent:
6,355,968 →
Application:
09/638,722 →
Method for Generating a Sequence of Random Number of a 1/F- Nose
Patent:
6,795,840 →
Application:
09/648,939 →
Level-Shifting Circuitry Having "High" Output Impedance During Disable Mode
Patent:
6,853,233 →
Application:
09/659,872 →
Combined tracking of wll and vpp with low threshold voltage in dram array
Patent:
6,381,182 →
Application:
09/659,946 →
Method and Apparatus for Fast Automated Failure Classification for Semiconductor Wafers
Patent:
6,963,813 →
Application:
09/660,703 →
Semiconductor Structure and Method of Fabrication
Patent:
6,373,135 →
Application:
09/662,691 →
Control of Separation Between Transfer Gate and Storage Node in Vertical Dram
Patent:
6,706,634 →
Application:
09/664,825 →
Level-Shifting Circuitry Having "Low" Output During Disable Mode
Patent:
6,501,298 →
Application:
09/664,826 →
Dual Thickness Gate Oxide Fabrication Method Using Plasma Surface Treatment
Patent:
6,573,192 →
Application:
09/667,053 →
Trench Capacitor Memory Cell
Patent:
6,812,091 →
Application:
09/669,585 →
Level-Shifting Circuitry Having "High" Output During Disable Mode
Patent:
6,459,300 →
Application:
09/671,915 →
Integrated Circuit Comprising a Self Aligned Trench, and Method of Forming Thereof
Patent:
6,537,870 →
Application:
09/675,432 →
Area Efficient Method for Programming Electrical Fuses
Patent:
6,426,911 →
Application:
09/691,953 →
Nitrogen Implantation Using a Shadow Effect to Control Gate Oxide Thickness in Dram Semiconductor
Patent:
6,967,147 →
Application:
09/714,356 →
Method for forming and filling isolation trenches
Patent:
6,294,423 →
Application:
09/718,211 →
Two Step Chemical Mechanical Polishing Process
Patent:
6,593,240 →
Application:
09/723,802 →
Circuit for Receiving and Driving a Clock-Signal
Receiver Immune to Slope-Reversal Noise
Dram with Vertical Transistor and Trench Capacitor Memory Cells and Method of Fabrication
Method for Fabricating Transistors Having Damascene Formed Gate Contacts and Self-Aligned Borderless Bit Line Contacts
System and Method for Improved Throughput of Semiconductor Wafer Processing
Area Efficient Stacking of Antifuses in Semiconductor Device
Conductive Lines with Reduced Pitch
Multi-Layer Pt Electrode for Dram and Fram with High K Dielectric Materials
Method for Manufacturing a Conductor Structure for an Integrated Circuit
Bis-O-Aminophenols and O-Aminophenolcarboxylic Acids and Process for Preparing the Same
Method for Reading Nonvolatile Semiconductor Memory Configurations
Method for fabricating a contact layer
Method for Setting the Threshold Voltage of a Mos Transistor
Method for Fabricating and Checking Structures of Electronic Circuits in a Semiconductor Substrate
An Mram Memory with Drive Logic Arrangement
Trench Capacitor and Method for Fabricating a Trench Capacitor
Mask for Optical Projection Systems, and a Process for Its Production
Method for Fabricating a Wiring Plane on a Semiconductor Chip with an Antifuse
Method for Removing Structures
Component Holder for Testing Devices and Component Holder System Microlithography
Amplifier Circuit
Method for Making Electrical Contact with a Rear Side of a Semiconductor Substrate During Its Processing
Dram Memory Cell for Dram Memory Device and Method for Manufacturing It
Method for Monitoring Nitrogen Processes
Method for Fabricating a Barrier Layer
Electronic Device and Method for Fabricating an Electronic Device
Integrated Circuit with Test Mode, and Test Configuration for Testing an Integrated Circuit
Integrated Memory Having Memory Cells with Magnetoresistive Memory Effect
Method of Fabricating a Dielectric Antifuse Structure
Connection Element
Semiconductor Component and Corresponding Fabrication Process
Circuit Configuration for Equalizing Different Voltages on Line Runs in Integrated Semiconductor Circuits
Integrated Circuit Having a Timing Circuit, and Method for Adjustment of an Output Signal from the Timing Circuit
Current Driver Configuration for Mram
Circuit Configuration for Switching Over a Receiver Circuit in Particular in Dram Memories and Dram Memory Having the Circuit Configuration
Mram Configuration
Chip Id Register Configuration
Method and Configuration for Compensating for Parasitic Current Losses
Method for Preventing Electromigration in an Mram
Metallization Arrangement for Semiconductor Structure and Corresponding Fabrication Method
Support Matrix for Integrated Semiconductors, and Method for Producing It
Support Matrix with Bonding Channel for Integrated Semiconductors, and Method for Producing It
Process for Producing a Doped Semiconductor Substrate
Random Access Semiconductor Memory with Reduced Signal Overcoupling
Integrated Semiconductor Memory Having Memory Cells in a Plurality of Memory Cell Arrays and Method for Repairing Such a Memory
Method of Inferring the Existence of Light by Means of a Measurement of the Electrical Characteristics of a Nanotube Bound with a Dye, and Detection Arrangement
Method and Device for Reading and for Checking the Time Position of Data Response Signals Read Out from a Memory Module to Be Tested
System for Testing Fast Integrated Digital Circuits, in Particular Semiconductor Memory Modules
Method for Testing a Device and a Test Configuration Including a Device with a Test Memory
Address Counter for Addressing Synchronous High-Frequency Digital Circuits, in Particular Memory Devices
Method and Device for Generating Digital Signal Patterns
Configuration for Implementing Redundancy for a Memory Chip
Circuit Configuration for Generating Control Signals for Testing High-Frequency Synchronous Digital Circuits
System for Testing Fast Synchronous Digital Circuits, Particularly Semiconductor Memory Chips
Method and Device for Testing Set-Up Time and Hold Time of Signals of a Circuit with Clocked Data Transfer
Buffer Device
Circuit Configuration
Method, System, and Method of Using a Component for Setting the Electrical Characteristics of Microelectronic Circuit Configurations
Method for Forming a Trench in a Semiconductor Substrate
Method for Forming an Insulator Having a Low Dielectric Constant on a Semiconductor Substrate
Control System and Methods for Photolithographic Processes
Method for Fabricating Capacitor Electrodes
Circuit Configuration for Deactivating Word Lines in a Memory Matrix
Method and Device for Producing a Metal/Metal Contact in a Multilayer Metallization of an Integrated Circuit
Soi Substrate, a Semiconductor Circuit Formed in a Soi Substrate, and an Associated Production Method
Device for Cleaning a Wafer of Abrasive Agent Suspension Remaining After Polishing with Brushes and Di Water
Method and Apparatus for Temporally Correcting a Data Signal
Electronic Device Having Stacked Modules and Method for Producing It
Wafer Cleaning Apparatus
Method for Farbricating Field-Effect Transistors in Integrated Semiconductor Circuits and Integrated Semiconductor Circuit Fabricated with a Field-Effect Transistor of This Type
Mram Module Configuration
Electronic Devices and a Sheet Strip for Packaging Bonding Wire Connections of Electronic Devices and Method for Producing Them
Method for Detecting and Automatically Eliminating Phase Conflicts on Alternating Phase Masks
Configuration for Fuse Initialization
Method for Masking Dq Bits
Circuit Configuration for Generating Sense Amplifier Control Signals
Lithography Mask Configuration
Method for Fabricating an Integrated Semiconductor Product
Polybenzoxazole Precursors, Photoresist Solution, Polybenzoxazole, and Process for Preparing a Polybenzoxazole Precursor
Voltage Supply for Semiconductor Memory Arrangement
Integrated Circuit Having a Data Processing Unit and a Buffer Memory
Method for Determining the Distance Between Periodic Structures on an Integrated Circuit or a Photomask
Electronic Component with Stacked Semiconductor Chips and Method of Producing the Component
Reaction Chamber for Processing a Substrate Wafer, and Method for Operating the Chamber
Electronic Component with a Semiconductor Chip and Method of Producing the Electronic Component
Electronic Component with a Semiconductor Chip and Method of Producing an Electronic Component
Integrated Semiconductor Memory Device
Method of Fabricating a Patterned Metal-Containing Layer on a Semiconductor Wafer
Semiconductor Memory Cell and Method of Fabricating a Semiconductor Memory Cell
Semiconductor Memory Cell and Semiconductor Component as Well as Manufacturing Methods Therefore
Integrated Semiconductor Circuit Having Transistors That Are Switched with Different Frequencies
Method for Chemical-Mechanical Polishing of Layers Made from Metals from the Platinum Group
Method for Producing Scatter Lines in Mask Structures for Fabricating Integrated Electrical Circuits
Test Method and Test Device for Electronic Memories
Field Effect Transistor
Vertical Transistor and Transistor Fabrication Method
Contact Spring Configuration for Contacting a Semiconductor Wafer and Method for Producing a Contact Spring Configuration
Leadframe for Semiconductor Chips and Electronic Devices and Production Methods for a Leadframe and for Electronic Devices
Method for Determining the Ability to Project Images of Integrated Semiconductor Circuits Onto Alternating Phase Masks
Field-Effect Transistor, Circuit Configuration and Method of Fabricating a Field-Effect Transistor
Apparatus and Method for Populating Transport Tapes
Method of Patterning Ferroelectric Layers
Method for Fabricating a Trench Capacitor
Method for fabricating an integrated semiconductor component
Semiconductor Configuration and Process for Etching a Layer of the Semiconductor Configuration Using a Silicon-Containing Etching Mask
Method for Making Contact with a Doping Region of a Semiconductor Component
Patent:
6,855,630 →
Application:
10/614,430 →
Semiconductor Component with Esd Protection
Method to Etch Poly Si Gate Stacks with Raised Sti Structure
Process for Producing and Removing a Mask Layer
Configuration and Method for Making Contact with the Back Surface of a Semiconductor Substrate
Method of Fabricating an Electronic Component
Method for Fabricating a Mosfet Having a Very Small Channel Length
Method for Providing Error Information Relating to Inconsistencies in a System of Differential Equations
Multi-Layer Electrode and Method of Forming the Same
Method of Producing an Electronic Component
Level-Shifting Circuitry Having "High" Output Impedance During Disable Mode
Method of Implanting Using a Shadow Effect
Related Assignments
(9)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES RICHMOND, LP
To: QIMONDA AG
Reel/Frame 023792/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023828/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023773/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON AG
To: QIMONDA AG
Reel/Frame 023774/0001 →
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES NORTH AMERICA CORP
To: QIMONDA AG
Reel/Frame 023774/0399 →
Assignment of Assignor's Interest
Jan 14, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0401 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Feb 12, 2020
From: POLARIS INNOVATIONS LIMITED
To: CHANGXIN MEMORY TECHNOLOGIES, INC
Reel/Frame 051917/0581 →