Metallization arrangement for semiconductor structure and corresponding fabrication method
View Patent ↗The present invention provides a metallization arrangement for a semiconductor structure ( 1 ) having a first substructure plane (M 1 ), preferably a first metallization plane; a second metallization plane (M 2 ) having a first and a second adjacent interconnect (LBA; LBB); a first intermediate dielectric (ILD 1 ) for mutual electrical insulation of the first substructure plane (M 1 ) and second metallization plane (M 2 ); and via holes (V) filled with a conductive material (FM) in the intermediate dielectric (ILD 1 ) for connecting the first substructure plane (M 1 ) and second metallization plane (M 2 ). A liner layer (L) made of a dielectric material is provided under the second metallization plane (M 2 ), which liner layer is interrupted in the interspace (O) between the first and second adjacent interconnects (LBA; LBB) of the second metallization plane (M 2 ). The invention likewise provides a corresponding fabrication method.
1. A method for fabricating a metallization arrangement for a semiconductor structure, said method comprising:
providing a first metallization plane on said semiconductor structure;
providing a first intermediate dielectric on said first metallization plane, said first intermediate dielectric having a first dielectric constant;
providing a liner layer made of a dielectric material on said first intermediate dielectric, said liner having a second dielectric constant that is greater than the first dielectric constant;
providing via holes in said first intermediate dielectric and said liner layer, said via holes being filled with a conductive material, thereby completing a first resulting structure;
providing a second metallization plane on said first resulting structure, said liner layer acting as a diffusion barrier for the second metallization plane;
patterning first and second interconnects in said second metallization plane thereby forming an interspace between said first and second interconnects; and
completely interrupting said liner layer in said interspace between said first interconnect and said second interconnect such that said liner layer is removed everywhere that the second metallization plane is removed, in order to prevent capacitive coupling between said first and second interconnects.
2. The method as claimed in claim 1 , wherein patterning and interrupting are carried out in a common etching step.
3. The method as claimed in claim 1 , further comprising providing an electrical circuit integrated into a silicon substrate.
4. The method as claimed in claim 3 , wherein providing a liner layer comprises fabricating said liner layer from a material selected from the group consisting of silicon dioxide and silicon nitride.
5. The method as claimed in claim 4 , wherein said patterning is carried out in a first metal etching step and said interrupting is carried out in a second silicon dioxide etching step.
6. The method as claimed in claim 1 , further comprising providing a dielectric in said interspace.
7. The method as claimed in claim 1 , further comprising providing a mask on said second metallization plane for use in patterning and interrupting.