Patent Assignment
Reel/Frame 023792/0001
Assignment of Assignor's Interest
Recorded: 2010-01-13
Pages: 387
Assignor
INFINEON TECHNOLOGIES RICHMOND, LP
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties
(52)
In-Situ Method for Preparing and Highlighting of Defects for Failure Analysis
Patent:
6,162,735 →
Application:
09/277,673 →
Yield Prediction and Statistical Process Control Using Predicted Defect Related Yield Loss
Patent:
6,496,958 →
Application:
09/299,979 →
Double Gated Transistor
Patent:
6,459,123 →
Application:
09/302,768 →
Efficient Redundancy Calculation System and Method for Various Types of Memory Devices
Patent:
6,725,403 →
Application:
09/432,064 →
Advanced Bit Fail Map Compression with Fail Signature Analysis
Patent:
6,564,346 →
Application:
09/455,855 →
Usage of Redundancy Data for Displaying Failure Bit Maps for Semiconductor Devices
Patent:
6,499,120 →
Application:
09/476,450 →
Uniform Recess Depth of Recessed Resist Layers in Trench Structure
Patent:
6,482,716 →
Application:
09/481,769 →
Method for Detecting and Classifying Scratches Occuring During Wafer Semiconductor Processing
Patent:
6,493,645 →
Application:
09/481,770 →
Folded Deep Trench Capacitor and Method
Patent:
6,417,063 →
Application:
09/599,824 →
Method and System for Semiconductor Testing Using Yield Correlation Between Global and Class Parameters
Patent:
6,434,725 →
Application:
09/603,592 →
Method for High Speed Testing with Low Speed Semiconductor Test Equipment
Patent:
6,718,487 →
Application:
09/604,220 →
Automated bad socket masking in real-time for test handlers
Patent:
6,400,134 →
Application:
09/619,075 →
Method and Apparatus for Fast Automated Failure Classification for Semiconductor Wafers
Patent:
6,963,813 →
Application:
09/660,703 →
Double Gated Transistor
Patent:
6,503,784 →
Application:
09/670,742 →
System and Method for Improved Throughput of Semiconductor Wafer Processing
Method for Reading Semiconductor Die Information in a Parallel Test and Burn-in System
Dry Polymer and Oxide Veil Removal for Post Etch Cleaning
Patent:
6,479,396 →
Application:
09/794,055 →
On-chip circuits for high speed memory testing with a slow memory tester
Patent:
6,404,250 →
Application:
09/819,588 →
Apparatus and Process for Collecting Trace Metals from Wafers
Method and Apparatus for Collecting and Displaying Bit-Fail-Map Information
Electrostatic Damage (Esd) Protected Photomask
Pseudo Fail Bit Map Generation for Rams During Component Test and Burn-in in a Manufacturing Environment
Memory Employing Multiple Enable/Disable Modes for Redundant Elements and Testing Method Using Same
Patent:
6,490,209 →
Application:
09/968,749 →
System and Method for Storing Parity Information in Fuses
Sti Leakage Reduction
System and Method for Enhanced Monitoring of an Etch Process
Fuse Configuration with Modified Capacitor Border Layout for a Semiconductor Storage Device
Current Measurement Circuit and Method for Voltage Regulated Semiconductor Integrated Circuit Devices
Memory Employing Multiple Enable/Disable Modes for Redundant Elements and Testing Method Using Same
Dram Having Improved Leakage Performance and Method for Making Same
Method of Forming a Gate Contact in a Semiconductor Device
Rapid Deposition of Borosilicate Glass Films
Anti-Reflective Coating Conformality Control
Method and Device for Minimizing Multi-Layer Microscopic and Macroscopic Alignment Errors
Acoustic Detection of Mechanically Induced Circuit Damage
Method of Calculating a Pressure Compensation Recipe for a Semiconductor Wafer Implanter
Utilization of an Ion Gauge in the Process Chamber of a Semiconductor Ion Implanter
Deep Trench Capacitor Having Increased Surface Area
Method of and System for Analyzing Cells of a Memory Device
Post Metal Chemical Mechanical Polishing Dry Cleaning
Method of Determining the Overlay Accuracy of Multiple Patterns Formed on a Semiconductor Wafer
Method of Removing Pecvd Residues of Fluorinated Plasma Using in-Situ H2 Plasma
Method and Arrangement for Controlling Focus Parameters of an Exposure Tool
Process for Fabricating a Semiconductor Device Having Deep Trench Structures
Edge Protection Process for Semiconductor Device Fabrication
Eliminating Systematic Process Yield Loss via Precision Wafer Placement Alignment
Deglaze Route to Compensate for Film Non-Uniformities After Sti Oxide Processing
Lithography Method and System with Correction of Overlay Offset Errors Caused by Wafer Processing
System and Method to Predict the State of a Process Controller in a Semiconductor Manufacturing Facility
Patent:
7,127,304 →
Application:
11/131,957 →
Method and Apparatus for Automated Beam Optimization in a Scanning Electron Microscope
Method and Apparatus for Monitoring Precision of Wafer Placement Alignment
Post Metal Chemical Mechanical Polishing Dry Cleaning
Related Assignments
(6)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036539/0196 →
Assignment of Assignor's Interest
Sep 9, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036575/0368 →
Assignment of Assignor's Interest
Oct 7, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036808/0284 →
Assignment of Assignor's Interest
Oct 8, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036818/0583 →
Assignment of Assignor's Interest
Feb 12, 2020
From: POLARIS INNOVATIONS LIMITED
To: CHANGXIN MEMORY TECHNOLOGIES, INC
Reel/Frame 051917/0581 →