Patent Assignment
Reel/Frame 036808/0284
Assignment of Assignor's Interest
Recorded: 2015-10-07
Received: 2015-10-07
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IEX, IRELAND
Covered Properties
(100)
Integrated Read-Only Memory, Method for Operating Said Read-Only Memory and Corresponding Production Method
Application:
10/505,320 →
Semiconductor Arrangement Comprising Transistors Based on Organic Semiconductors and Non-Volatile Read-Write Memory Cells
Application:
10/495,614 →
Method and Device for Testing Semiconductor Memory Devices
Application:
10/487,255 →
Circuit Arrangement for Reading Out, Evaluating and Reading in Again a Charge State into a Memory Cell
Application:
10/944,536 →
Data Carrier Card
Application:
10/925,882 →
Semiconductor Memory Cell Having a Trench and a Planar Selection Transistor and Method for Producing the Same
Application:
10/913,797 →
Memory Cell with Trench Capacitor and Vertical Select Transistor and an Annular Contact-Making Region Formed Between Them
Application:
10/486,758 →
Dram Memory Cell with a Trench Capacitor and Method for Production Thereof
Application:
10/479,522 →
Circuit Element Having a First Layer of an Electrically Insulating Substrate Material and Method for Manufacturing a Circuit Element
Application:
10/857,635 →
Method of Forming a Silicon Dioxide Layer
Application:
10/823,607 →
Method for Measuring a Characteristic Dimension of at Least One Pattern on a Disc -Shaped Object in a Measuring Instrument
Application:
10/802,728 →
Phase-Shift Mask
Application:
10/787,118 →
Method of Removing Pecvd Residues of Fluorinated Plasma Using in-Situ H2 Plasma
Application:
10/786,996 →
Method for Providing Bitline Contacts in a Memory Cell Array and a Memory Cell Array Having Bitline Contacts
Application:
10/724,903 →
Production Method for a Semiconductor Component
Application:
10/477,620 →
Method for the Planarization of a Semiconductor Structure
Application:
10/692,234 →
Method for Fabricating a Vertical Transistor, and Semiconductor Memory Cell Having a Trench Capacitor and an Associated Vertical Selection Transistor
Application:
10/626,956 →
Method for Producing a Mask Set for Lithography Including at Least One Mask and Methods for Imaging Structures of a Predetermined Layout into a Common Exposure Plane
Application:
10/439,193 →
Method for Testing an Electronic Component; Computer Program Product, Computer Readable Medium, and Computer Embodying the Method; and Method for Downloading the Program Embodying the Method
Application:
10/431,900 →
Method for Fabricating a Memory Cell
Application:
10/378,101 →
Addressing Device for Selecting Regular and Redundant Elements
Application:
10/364,014 →
Memory Module with Improved Electrical Properties
Application:
10/360,456 →
Method of Checking Electrical Connections Between a Memory Module and a Semiconductor Memory Chip
Application:
10/356,921 →
Method for Producing a Cavity in a Monocrystalline Silicon Substrate and a Semiconductor Component Having a Cavity in a Monocrystalline Silicon Substrate with an Epitaxial Covering Layer
Application:
10/348,150 →
Photomask and Method of Structuring a Photoresist by Double Exposure with Imaging Auxiliary Structures and Different Exposure Tools
Application:
10/331,641 →
Process Facility Having at Least Two Physical Units Each Having a Reduced Density of Contaminating Particles with Respect to the Surroundings
Application:
10/330,444 →
Contact Pin for Testing Microelectronic Components Having Substantially Spherical Contacts
Application:
10/320,127 →
Method for Operating a Semiconductor Memory, and Semiconductor Memory
Application:
10/317,972 →
Method for Fabricating an Integrated Semiconductor Circuit
Application:
10/310,397 →
Layer Arrangement, Memory Cell, Memory Cell Arrangement and Method for Producing a Layer Arrangement
Application:
10/314,049 →
Integrated Memory and Method of Repairing an Integrated Memory
Application:
10/304,135 →
Method and Semiconductor Wafer Configuration for Producing an Alignment Mark for Semiconductor Wafers
Application:
10/301,393 →
Semiconductor Memory Module with Low Current Consumption
Application:
10/301,398 →
Semiconductor Component
Application:
10/301,368 →
Reflection Mask and Method for Fabricating the Reflection Mask
Application:
10/298,429 →
Device and Method for Associating Information Concerning Memory Cells of a Memory with an External Memory
Application:
10/298,970 →
Sige Vertical Gate Contact for Gate Conductor Post Etch Treatment
Application:
10/298,717 →
Circuit Device Having a Fuse
Application:
10/293,923 →
Reflection Mask for Euv-Lithography and Method for Fabricating the Reflection Mask
Application:
10/292,866 →
Method for Fabricating a Mask for Semiconductor Structures
Application:
10/291,070 →
Method for Precharging Memory Cells of a Dynamic Semiconductor Memory During Power-Up and Semiconductor Memory
Application:
10/289,913 →
Memory Device and Method of Accessing a Memory Device
Application:
10/290,365 →
Line Configuration for Bit Lines for Contact-Connecting at Least One Memory Cell, Semiconductor Component with a Line Configuration and Method for Fabricating a Line Configuration
Application:
10/288,387 →
Integrated Memory, and a Method of Operating an Integrated Memory
Application:
10/287,501 →
Method for Producing an Electronic Component Having a Plurality of Chips That Are Stacked One Above the Other and Contact-Connected to One Another
Application:
10/285,924 →
Method for Reducing the Contact Resistance in Organic Field-Effect Transistors by Applying a Reactive Intermediate Layer Which Dopes the Organic Semiconductor Layer Region-Selectively in the Contact Region
Application:
10/285,049 →
Process for Silylating Photoresists in the Uv Range
Application:
10/285,050 →
Process for Structuring a Photoresist by Uv at Less Than 160 Nm and Then Aromatic and/or Alicyclic Amplification
Application:
10/285,052 →
Charge Trapping Memory Cell, Method for Fabricating It, and Semiconductor Memory Device
Application:
10/283,857 →
Floating Gate Memory Cell, Method for Fabricating It, and Semiconductor Memory Device
Application:
10/283,913 →
Fabrication Method and Apparatus for Fabricating a Spatial Structure in a Semiconductor Substrate
Application:
10/281,697 →
Method for Testing a Plurality of Devices Disposed on a Wafer and Connected by a Common Data Line
Application:
10/278,227 →
Memory cell, wafer, semiconductor component with memory cell having insulation collars and method for fabricating an insulating collar for a memory cell
Application:
10/277,387 →
Method and Computer System for Structural Analysis and Correction of a System of Differential Equations Described by a Computer Language
Application:
10/273,520 →
Method of Forming a Vertical Field-Effect Transistor Device
Application:
10/272,386 →
Method for Fabricating a Microcontact Spring on a Substrate
Application:
10/267,224 →
Process for Etching a Metal Layer System
Application:
10/267,335 →
Digital Memory Circuit Having a Plurality of Memory Areas
Application:
10/266,355 →
Digital Memory Circuit Having a Plurality of Segmented Memory Areas
Application:
10/266,190 →
Circuit Configuration for Processing Data, and Method for Identifying an Operating State
Application:
10/266,354 →
Memory Device
Application:
10/266,353 →
Storage Cell Field and Method of Producing the Same
Application:
10/266,188 →
Method of Fabricating a Microstructure and Photolithography Trimming Mask
Application:
10/262,117 →
Poly-O-Hydroxyamides, Polybenzoxazoles, Processes for Producing Poly-O-Hydroxyamides, Processes for Producing Polybenzoxazoles, Dielectrics Including a Polybenzoxazole, Electronic Components Including the Dielectrics, and Processes for Manufacturing the Electronic
Application:
10/261,034 →
Data Processing System for Designing a Layout of an Integrated Electronic Circuit Having a Multiplicity of Electronic Components and Method of Designing a Layout
Application:
10/261,194 →
Semiconductor Memory Device
Application:
10/260,899 →
Scalable Driver Device and Related Integrated Circuit
Application:
10/261,200 →
Method for Integrating Imperfect Semiconductor Memory Devices in Data Processing Apparatus
Application:
10/254,694 →
Method for Replacing Defective Memory Cells in Data Processing Apparatus
Application:
10/253,465 →
Apparatus for Signaling That a Predetermined Time Value Has Elapsed
Application:
10/253,793 →
Electronic Circuit with a Driver Circuit
Application:
10/253,001 →
Method for Operating a Semiconductor Memory and Semiconductor Memory
Application:
10/247,572 →
Method of Insulating Interconnects, and Memory Cell Array with Insulated Interconnects
Application:
10/247,576 →
Method for Rewiring Pads in a Wafer-Level Package
Application:
10/247,575 →
Circuit Configuration for Receiving a Data Signal
Application:
10/247,577 →
Wafer with Additional Circuit Parts in the Kerf Area for Testing Integrated Circuits on the Wafer
Application:
10/247,574 →
Method for Testing Integrated Semiconductor Memory Devices
Application:
10/245,626 →
Method of Attaching Semiconductor Devices on a Switching Device and Such an Attached Device
Application:
10/244,256 →
Evaluation Configuration for Semiconductor Memories
Application:
10/244,258 →
Photosensitive Formulation for Buffer Coatings, Film Containing the Photosensitive Formulation, and Method for Fabricating Electronics with the Photosensitive Formulation
Application:
10/244,257 →
Bis-O-Aminophenol Derivatives, Poly-O-Hydroxyamides, and Polybenzoxazoles, Usable in Photosensitive Compositions, Dielectrics, Buffer Coatings, and Microelectronics
Application:
10/244,839 →
Mark Configuration, Wafer with at Least One Mark Configuration and Method for the Fabrication of at Least One Mark Configuration
Application:
10/244,281 →
Bis-O-Nitrophenols Derivatives and Poly-O-Hydroxyamides, Polybenzoxazoles, Materials, and Microelectronic Devices Made Therefrom
Application:
10/244,301 →
Polybenzoxazoles from Poly-O-Hydroxyamide, Novel Poly-O-Hydroxyamides, Preparation Processes Therefor, and Their Application in Microelectronics
Application:
10/244,802 →
Integrated Circuit Having a Current Measuring Unit
Application:
10/243,067 →
Method of Connecting a Device to a Support, and Pad for Establishing a Connection Between a Device and a Support
Application:
10/241,546 →
Method of Testing a Mapping of an Electrical Circuit
Application:
10/238,819 →
Electronic Device Having a Trimming Possibility and at Least One Semiconductor Chip and Method for Producing the Electronic Device
Application:
10/238,940 →
Output Driver Circuit and Method for Adjusting a Driver Device
Application:
10/235,050 →
Method for Adjusting a Multilevel Phase-Shifting Mask or Reticle
Application:
10/233,970 →
Method and Device for Sorting Wafers
Application:
10/234,077 →
Volatile Semiconductor Memory and Mobile Device
Application:
10/233,968 →
Silicon Resist for Photolithography at Short Exposure Wavelengths and Process for Making Photoresists
Application:
10/233,915 →
Apparatus for Measuring Parasitic Capacitances on an Integrated Circuit
Application:
10/234,079 →
Method for Optimizing and Method for Producing a Layout for a Mask, Preferably for Use in Semiconductor Production, and Computer Program Therefor
Application:
10/233,691 →
Method for Planarizing an Isolating Layer
Application:
10/233,686 →
Method for Adjusting and Exposing the Second Level of a Phase-Shift Mask
Application:
10/233,701 →
Electronic Circuit for Generating an Output Voltage Having a Defined Temperature Dependence
Application:
10/234,078 →
Method of Fabricating a Trench-Structure Capacitor Device
Application:
10/233,690 →
Method for Producing a Structured Layer on a Semiconductor Substrate
Application:
10/233,692 →