Integrated read-only memory, method for operating said read-only memory and corresponding production method
View Patent ↗An integrated read-only memory having select transistors, each of which has a drain connection and an electrode connection for feeding an electrical signal such as a voltage or a current. A layer is provided between the drain connections and the electrode, whose electric resistance can be changed under the effect of a configuration voltage or current. The layer may be applied in a backend process.
1. An integrated read-only memory, comprising:
selection transistors, each selection transistors having a drain connection; an electrode for feeding a voltage or a current;
a common layer between the drain connections and the electrode electrically linking the drain connections to the electrode, wherein the electrical resistance of the common layer is changeable by a configuration voltage or a configuration current;
a source connection per selection transistor; and
a bit line that is electrically connected to at least one source connection.
2. The read-only memory of claim 1 , wherein resistance of the common layer is configured to be switched over.
3. The read-only memory of claim 1 or 2 , wherein the resistance of the common layer is switchable between two resistance characteristic curves.
4. The read-only memory of claim 1 further comprising:
a read voltage applied to the common layer or a read current fed to the layer within a defined voltage or current range in a read Operation of the read-only memory, and
a configuration voltage or a configuration current outside the voltage or current range provided for the read Operation in a configuration operation of the read-only memory.
5. The read-only memory of claim 1 , wherein the read-only memory comprises a flash memory.
6. The read-only memory of claim 1 , wherein the selection transistors are arranged in an array.
7. The read-only memory of claim 1 , wherein the bit line is connected to a decoder circuit.
8. The read-only memory of claim 1 , wherein the bit line is accessible for an external connection.
9. The read-only memory of claim 1 , further comprising: a gate connection per selection transistor, and a word line that is electrically connected to at least one gate connection.
10. The read-only memory of claim 9 , wherein the word line is connected to a decoder circuit.
11. The read-only memory of claim 9 , wherein the word line is accessible for an external connection.
12. The read-only memory of claim 1 , wherein the selection transistors have a planar construction in the substrate.
13. The read-only memory of claim 1 , wherein the selection transistors have a vertical construction in the substrate.
14. The read-only memory of claim 1 , wherein the common layer comprises a molecular layer.
15. The read-only memory of claim 14 , wherein the common layer includes rotaxane.
16. The read-only memory of claim 14 , wherein the common layer includes catenane.
17. The read-only memory of claim 14 , wherein the common layer includes a bispyridinium compound.
18. The read-only memory of claim 1 , wherein the common layer comprises a dielectric.
19. The read-only memory of claim 18 , wherein the common layer includes SrZrO 3 .
20. The read-only memory of claim 1 , wherein the common layer comprises a polymer.
21. The read-only memory of claim 20 , wherein the common layer includes 3-nitrobenzal malonitrile, 1,4-phenylenediamine complex.
22. The read-only memory of claim 20 , in which the common layer includes a chalcogenide compound.
23. A method for operating an integrated read-only memory comprising selection transistors, each selection transistor having a drain connection; an electrode for feeding a voltage or a current; a common layer between the drain connections and the electrode electrically linking the drain connections to the electrode, the electrical resistance of the layer is changeable by a configuration voltage or a configuration current; a source connection per selection transistor; and a bit line that is electrically connected to at least one source connection, the method comprising:
applying, in a read operation, a read voltage or a read current within a defined voltage or current range is applied to the common layer; and
applying, in a configuration operation, a configuration voltage or a configuration current outside the voltage or current range provided for the read operation to the common layer.
24. A method for producing an integrated read-only memory, the method comprises:
producing selection transistors, each selection transistor having a drain contact;
arranging an electrode;
providing a common layer between the drain connections and the electrode electrically linking the drain connections to the electrode, wherein the electrical resistance of the common layer is changeable by a configuration voltage or a configuration current;
forming a source connection per selection transistor; and
forming a bit line which is electrically connected to at least one source connection.
25. The method for producing an integrated read-only memory of claim 24 , wherein the selection transistors are produced in a front end process.
26. The method for producing an integrated read-only memory of claim 24 , wherein the common layer is deposited in a back end process.
27. The method for producing an integrated read-only memory of claim 24 , wherein the selection transistors are constructed in planar fashion in the substrate.
28. The method for producing an integrated read-only memory of claim 24 , wherein the selection transistors are constructed vertically in the substrate.
29. The method for producing an integrated read-only memory of claim 24 , wherein providing a common layer comprises providing a molecular layer.
30. The method for producing an integrated read-only memory of claim 29 , wherein the common layer includes rotaxane.
31. The method for producing an integrated read-only memory of claim 29 , wherein the common layer includes catenane.
32. The method for producing an integrated read-only memory of claim 29 , wherein the common layer includes a bispyridinium compound.
33. The method for producing an integrated read-only memory of claim 24 , wherein providing a common layer comprises providing a dielectric.
34. The method for producing an integrated read-only memory of claim 33 , wherein the common layer includes SrZrO 3 .
35. The method for producing an integrated read-only memory of 24 , wherein providing a common layer comprises providing a polymer.
36. The method for producing an integrated read-only memory of claim 35 , wherein the common layer includes a 3-nitrobenzal malonitrile, 1.4-phenylenediamine complex.
37. The method for producing an integrated read-only memory of claim 28 , wherein the common layer includes a chalcogenide compound.
38. The method for producing an integrated of claim 24 , wherein the selection transistors are produced using CMOS technology.