Method of forming a gate contact in a semiconductor device
View Patent ↗A processing sequence for definition of gate contacts can be implemented using either a deep ultra-violet (DUV) or mid ultra-violet (MUV) positive resist processing and supports the use of a reticle that integrates contacts to various regions including gates, sources and drains of various devices. In a one example, the wafer is coated with a planarizing anti-reflective coating (ARC), which then supports imaging of gate contacts using a positive DUV or MUV resist. This processing allows the nitride cap of certain transistor gates to be replaced with an oxide. In this example, the ARC can serve as an etch guide for selective removal of a film.
1. A semiconductor device comprising:
a semiconductor region;
a first transistor disposed in the semiconductor region, the first transistor including:
a source region;
a drain region separated from the source region by a channel region;
a gate region overlying the channel region and being insulated therefrom;
a nitride layer overlying and physically contacting the entire gate region; and
a second transistor disposed in the semiconductor region, the second transistor including:
a source region;
a drain region separated from the source region by a channel region;
a gate region overlying the channel region and being insulated therefrom;
a conductive contact electrically contacting a first portion of the gate region;
an oxide layer abutting the conductive contact and a second portion of the gate region.
2. The device of claim 1 wherein the nitride layer encapsulates the gate region of the first transistor.
3. The device of claim 1 and further comprising a second nitride layer abutting a third portion of the gate region of the second transistor.
4. The device of claim 1 and further comprising a capacitor electrically coupled to the first transistor.
5. The device of claim 4 wherein the capacitor includes a plate disposed within a trench, the trench formed within the semiconductor region.