Eliminating systematic process yield loss via precision wafer placement alignment

1. A method for processing a semiconductor substrate, the method comprising:

correlating yield loss for performance of a processing step in a semiconductor manufacturing process with mechanical placement of the semiconductor substrate;

based on the correlation, defining a nominal placement position;

based on the correlation, defining a placement precision tolerance; and

during subsequent performance of the processing step, placing semiconductor substrates at the normal placement position within the placement precision tolerance.

2. The method of claim 1 wherein the processing step comprises a plasma etching step and wherein the placement precision tolerance is less than or equal to ±0.05 mm from the nominal position.

3. The method of claim 1 further comprising: programming a substrate handling robot to place the semiconductor substrates at the nominal placement position within the placement tolerance.

4. The method of claim 1 wherein correlating yield loss comprises:

for a plurality of test substrates, performing the processing step;

identifying defects occurring during performance of the processing step and locations of the defects on the test substrates;

identifying alignment positions of the test substrates; and

associating the locations of the defects and the alignment positions.

5. The method of claim 1 further comprising determining the yield loss for performance of the processing step in the semiconductor manufacturing process.

6. The method of claim 1 wherein correlating yield loss comprises:

performing the process steps for a number of test substrates;

testing the test substrates to identify defects and location of the defects on the test substrates;

identifying respective alignment positions of the test substrates; and

associating the location of the defects with the alignment positions.

7. The method of claim 1 further comprising identifying patterns of defects with alignment positions.

8. The method of claim 1 wherein defining a nominal placement position comprises:

defining a position centered on a wafer support in a processing device.

9. The method of claim 1 wherein defining a nominal placement position comprises:

defining a position offset from a center of a wafer support in a processing device.

10. The method of claim 1 further comprising programming a wafer placement robot to place semiconductor substrates at the nominal position during the subsequent performance of the processing step.

11. A method for processing a semiconductor substrate, the method comprising:

processing a set of test wafers in a processing device;

identifying defects occurring in the test wafers during the processing of the test wafers to establish a yield loss;

identifying respective alignment positions or relative misalignments of the test wafers with respect to a wafer support during the processing of the test wafers to establish mechanical placement of respective test wafers;

correlating the yield loss with the mechanical placement of the test wafers;

based on the correlation, defining a nominal placement position for a production wafer with respect to the wafer support during subsequent processing of the production wafer in the processing device;

based on the correlation, defining a placement precision tolerance for the production wafer with respect to the wafer support during subsequent processing of the production wafer in the processing device; and

during subsequent processing in the processing device, placing production wafers substantially at the normal placement position within the placement precision tolerance.

12. The method of claim 11 further comprising:

using the nominal placement position, programming a wafer placement robot to place the production wafers during the subsequent processing in the processing device.

13. The method of claim 11 wherein defining a nominal placement position comprises identifying a position at a center of the safer support or offset from the center while accounting for the yield loss.