Patent Assignment
Reel/Frame 036908/0923
Assignment of Assignor's Interest
Recorded: 2015-10-21
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(214)
Scanning Tip Orientation Adjustment Method for Atomic Force Microscopy
Method of Fabricating a Bottle Trench and a Bottle Trench Capacitor
Semiconductor Memory Device Comprising Memory Cells with Floating Gate Electrode and Method of Production
Circuit Board and Method for Producing a Circuit Board
Semiconductor Chip with Flexible Contacts at a Face
Transistor, Memory Cell Array and Method of Manufacturing a Transistor
Non-Volatile Semiconductor Memory Device
Charge-Trapping Memory Cell and Charge-Trapping Memory Device
Resistive Memory Element
Memory Device, Memory Controller and Memory System Having Bidirectional Clock Lines
Memory System with Two Clock Lines and a Memory Device
Flexible Blender
Gate Layer Diode Method and Apparatus
Measuring Flare in Semiconductor Lithography
Combined Receiver and Latch
Dqs for Data from a Memory Array
Edge Protection Process for Semiconductor Device Fabrication
Simulating a Floating Wordline Condition in a Memory Device, and Related Techniques
Method and Apparatus Compensating for Frequency Drift in a Delay Locked Loop
Semiconductor Memory Having Tri-State Driver Device
Circuit Having Delay Locked Loop for Correcting Off Chip Driver Duty Distortion
Variable Delay Line Using Two Blender Delays
Method for Determining an Optimal Absorber Stack Geometry of a Lithographic Reflection Mask
Apparatus and Method for Making Ground Connection
Duty Distortion Detector
Semiconductor Memory System and Method for the Transfer of Write and Read Data Signals in a Semiconductor Memory System
Memory Access Using Multiple Sets of Address/Data Lines
Method for Full Wafer Contact Probing, Wafer Design and Probe Card Device with Reduced Probe Contacts
Flexible Internal Address Counting Method and Apparatus
Eliminating Systematic Process Yield Loss via Precision Wafer Placement Alignment
Random Access Memory Having Fast Column Access
Esd Protection Apparatus for an Electrical Device
Energy Adjusted Write Pulses in Phase-Change Memories
Multi-Pulse Reset Write Scheme for Phase-Change Memories
Patent:
7,031,181 →
Application:
10/995,644 →
Polyelectrolyte Dispensing Polishing Pad
Transistor Array for Semiconductor Memory Devices and Method for Fabricating a Vertical Channel Transistor Array
Circuit and Method for Transmitting a Signal
Charge-Trapping Memory Cell and Method for Production
Memory Module with a Clock Signal Regeneration Circuit and a Register Circuit for Temporarily Storing the Incoming Command and Address Signals
Memory Cell Array
Memory Device and Method of Manufacturing a Memory Device
Patent:
7,034,408 →
Application:
11/005,045 →
Method for Production of Charge-Trapping Memory Devices
Patent:
7,026,220 →
Application:
11/006,484 →
Integrated Dram Memory Device
Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (Dimm)
Stacked Dram Memory Chip for a Dual Inline Memory Module (Dimm)
Method for Fabricating Bottom Electrodes of Stacked Capacitor Memory Cells and Method for Cleaning and Drying a Semiconductor Wafer
Method for Fabricating Bottom Electrodes of Stacked Capacitor Memory Cells
Patent:
7,018,893 →
Application:
11/011,039 →
6F2 Access Transistor Arrangement and Semiconductor Memory Device
Method to Improve Current and Slew Rate Ratio of Off-Chip Drivers
Memory Circuit Receivers Activated by Enable Circuit
Memory Having Test Circuit
Memory Access Using Multiple Activated Memory Cell Rows
Delay Locked Loop Using Synchronous Mirror Delay
Memory Having Internal Column Counter for Compression Test Mode
Opto-Electronic Memory Element on the Basis of Organic Metalloporphyrin Molecules
Memory with Selectable Single Cell or Twin Cell Configuration
High Dielectric Constant Materials
Duty Cycle Corrector
Duty Cycle Detector with First, Second, and Third Values
Semiconductor Device
Internal Reference Voltage Generation for Integrated Circuit Testing
Storage Capacitor and Method of Manufacturing a Storage Capacitor
Semiconductor Device and a Method for Fabricating a Semiconductor Device
Patent:
7,026,547 →
Application:
11/040,176 →
Integrated Circuit Including a Memory Having Low Initial Latency
Method of Treating a Structured Surface
Method for Producing a Dielectric Material on a Semiconductor Device and Semiconductor Device
Test Data Topology Write to Memory Using Latched Sense Amplifier Data and Row Address Scrambling
Memory Device Having Components for Transmitting and Receiving Signals Synchronously
Duty Cycle Corrector
Methods and Apparatus for Implementing a Power Down in a Memory Device
Method for Interconnecting Semiconductor Components with Substrates and Contact Means
Dissociated Fabrication of Packages and Chips of Integrated Circuits
Integrated Circuit Having a Memory Including a Low-K Dielectric Material for Thermal Isolation
Enhanced Megasonic Based Clean Using an Alternative Cleaning Chemistry
Method and Apparatus for Semiconductor Testing Utilizing Dies with Integrated Circuit
Random Access Memory Including Selective Activation of Select Line
Method and System for Fabricating Free-Standing Nanostructures
Patent:
7,008,853 →
Application:
11/066,320 →
Chip Stack Employing a Flex Circuit
Optimizing Light Path Uniformity in Inspection Systems
Semiconductor Memory Having Charge Trapping Memory Cells and Fabrication Method Thereof
Data Strobe Synchronization for Dram Devices
Memory Device Having Off-Chip Driver Enable Circuit and Method for Reducing Delays During Read Operations
Semiconductor Memory
Method for Producing Chip Stacks and Chip Stacks Formed by Integrated Devices
Memory with Data Latching Circuit Including a Selector
Integrated Circuit with a Control Input That Can Be Disabled
Non-Volatile Memory Card with Autarkic Chronometer
Method for Fabricating a Semiconductor Device
Power Saving Refresh Scheme for Drams with Segmented Word Line Architecture
Stacked Die Package
Test Mode for Detecting a Floating Word Line
Phase Change Memory Cell with High Read Margin at Low Power Operation
Method of Manufacturing a Memory Device
Circuit Including a Deskew Circuit for Asymmetrically Delaying Rising and Falling Edges
Exposing a Semiconductor Wafer Using Two Different Spectral Wavelengths and Adjusting for Chromatic Aberration
Methods and Apparatus for Implementing Standby Mode in a Random Access Memory
Multi-Bit Virtual-Ground Nand Memory Device
Memory Device
Integrated Semiconductor Memory Device for Synchronizing a Signal with a Clock Signal
Technique to Read Special Mode Register
Transistor, Memory Cell Array and Method of Manufacturing a Transistor
Method for Setting a Second Rank Address from a First Rank Address in a Memory Module
System and Method to Predict the State of a Process Controller in a Semiconductor Manufacturing Facility
Patent:
7,127,304 →
Application:
11/131,957 →
Redistribution Layer with Microstrips
Parallel Data Path Architecture
Temperature Dependent Self-Refresh Module for a Memory Device
Method of Forming a Charge-Trapping Memory Device
Method and Apparatus for the Depth-Resolved Characterization of a Layer of a Carrier
Differential Chip Performance Within a Multi-Chip Package
Fuse Resistance Read-Out Circuit
Memory Module Having Memory Chips Protected from Excessive Heat
Method for Testing an Integrated Semiconductor Memory
Memory Circuit Having Memory Cells Which Have a Resistance Memory Element
Method for Fabricating a Capacitor
Technique to Suppress Bitline Leakage Current
Method for Producing a Mask Layout Avoiding Imaging Errors for a Mask
Integrated Semiconductor Memory
Integrated Semiconductor Memory with Test Circuit
Circuit and Method for Generating an Output Signal
Nonvolatile Memory Cell and Methods for Operating a Nonvolatile Memory Cell
Prestage for an Off-Chip Driver (Ocd)
Integrated Semiconductor Memory and Method for Operating an Integrated Semiconductor Memory
Method for Producing a Rewiring Printed Circuit Board
Flip-Chip Component
Sense Amplifier Organization for Twin Cell Memory Devices
Semi-Conductor Component, as Well as a Process for the in-or Output of Test Data
Semi-Conductor Component Test Device with Shift Register, and Semi-Conductor Component Test Procedure
Semi-Conductor Component Test Device, in Particular Data Buffer Component with Semi-Conductor Component Test Device, as Well as Semi-Conductor Component Test Procedure
Method for Fabricating a Semiconductor Structure
Semiconductor Component, Arrangement and Method for Characterizing a Tester for Semiconductor Components
Integrated Circuit Including Sub-Lithographic Structures
Integrated Semiconductor Memory Device Including Sense Amplifiers
Driver Circuit with Reduced Jitter Between Circuit Domains
Integrated Semiconductor Memory Device
Inputting and Outputting Operating Parameters for an Integrated Semiconductor Memory Device
Integrated Semiconductor Memory Device
Reversible Oxidation Protection of Microcomponents
Method of Making an Integrated Circuit, Including Forming a Contact
Methods for Repairing and for Operating a Memory Component
Method for Producing a Semiconductor Structure
Nonvolatile Memory Cell Arrangement
Output Driver Circuit and a Method of Transmitting an Electrical Signal via an Output Driver Circuit
Method for Transmission and Reception of a Data Signal on a Line Pair, as Well as a Transmission and Reception Circuit for This Purpose
Manufacturing Method with Self-Aligned Arrangement of Solid Body Electrolyte Memory Cells of Minimum Structure Size
Method for Testing Semiconductor Chips by Means of Bit Masks
Method for Testing Semiconductor Chips Using Register Sets
Semiconductor Memory System with a Variable and Settable Preamble
Method and System for Carrying Out a Process on an Integrated Circuit
Insertable Calibration Device
Input Circuit for an Integrated Circuit
Method for Activating a Plurality of Word Lines in a Refresh Cycle, and Electronic Memory Device
Voltage Supply Circuit, in Particular for a Dram Memory Circuit, as Well as a Method for Controlling a Supply Source
Method of Producing a Conductive Layer Including Two Metal Nitrides
Integrated Circuit
Method of Producing a Microelectronic Electrode Structure, and Microelectronic Electrode Structure
Memory Component and Addressing of Memory Cells
Memory Component Having a Novel Arrangement of the Bit Lines
Semiconductor Wafer with Test Structure
Chip Component and Method for Producing a Chip Component
Driver Circuit for Binary Signals
Means of Mounting for Electronic Components, Arrangement and Procedure
Integrated Charge Pump
Semiconductor Memory Device, System with Semiconductor Memory Device, and Method for Operating a Semiconductor Memory Device
Integrated Semiconductor Memory Device with Adaptation of the Evaluation Characteristic of Sense Amplifiers
Integrated Semiconductor Memory Device with Test Circuit for Sense Amplifier
Integrated Circuit Including a Memory Apparatus and Production Method
Integrated Semiconductor Memory and Method for Operating a Semiconductor Memory
Synchronous Parallel/Serial Converter
Integrated Memory Circuit and Method for Repairing a Single Bit Error
Non-Volatile Memory Cell for Storage of a Data Item in an Integrated Circuit
Substrate for an Fbga Semiconductor Component
Apparatus for Projecting a Pattern into an Image Plane
Memory Device and Method for Testing Memory Devices with Repairable Redundancy
Integrated Semiconductor Memory
Integrated Semiconductor Memory with Clock-Synchronous Access Control
Integrated Semiconductor Memory with Adjustable Internal Voltage
Control Unit for Deactivating and Activating the Control Signals
Test Apparatus and Method for Testing a Circuit Unit
Receiver Circuit
Dll Circuit for Providing an Adjustable Phase Relationship with Respect to a Periodic Input Signal
Miniaturized Detection Coil Former for Nmr Spectroscopy
Circuit for Producing a Data Bit Inversion Flag
Field Effect Transistor with Gate Spacer Structure and Low-Resistance Channel Coupling
Integrated Semiconductor Memory Having Sense Amplifiers Selectively Activated at Different Timing
Buffer Component for a Memory Module, and a Memory Module and a Memory System Having Such Buffer Component
Circuit for Data Bit Inversion
Contacting Device, Testing Method and Corresponding Production Method
Semiconductor Memory Component and Method for Testing Semiconductor Memory Components Having a Restricted Memory Area (Partial Good Memories)
Semiconductor Memory Component and Method for Testing Semiconductor Memory Components
Method and Device for Transmission of Adjustment Information for Data Interface Drivers for a Ram Module
Device in a Memory Circuit for Definition of Waiting Times
Method for Initialization of Electronic Circuit Units, and Electric Circuit
Simulating a Floating Wordline Condition in a Memory Device, and Related Techniques
Duty Cycle Corrector
Nonvolatile Memory Cell
Method and System for Performing Non-Local Geometric Operations for the Layout Design of a Semiconductor Device
Method for Determining an Optimal Absorber Stack Geometry of a Lithographic Reflection Mask
Energy Adjusted Write Pulses in Phase-Change Memories
Memory Cell Array
Electrical Circuit with a Nanostructure and Method for Producing a Contact Connection of a Nanostructure
Memory with Resistance Memory Cell and Evaluation Circuit
Method for Cleaning a Semiconductor Wafer
Method of Applying an Adhesive Layer on Thincut Semiconductor Chips of a Semiconductor Wafer
Phase Change Memory Cell with High Read Margin at Low Power Operation
Phase Change Memory Cell with High Read Margin at Low Power Operation
Storage Capacitor and Method of Manufacturing a Storage Capacitor
Memory Cell Array
High Dielectric Constant Materials
Energy Adjusted Write Pulses in Phase-Change Memory Cells
Stacked Die Package
Transistor Array for Semiconductor Memory Devices and Method for Fabricating a Vertical Channel Transistor Array
Memory Device
Method of Fabricating an Integrated Circuit Having a Memory Including a Low-K Dielectric Material
Semiconductor Memory Having Charge Trapping Memory Cells and Fabrication Method Thereof
Related Assignments
(7)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Sep 3, 2015
From: INTERNATIONAL BUSINESS MACHINES CORPORATION
To: GLOBALFOUNDRIES U.S. 2 LLC
Reel/Frame 036550/0001 →
Assignment of Assignor's Interest
Oct 5, 2015
From: GLOBALFOUNDRIES U.S. 2 LLC; GLOBALFOUNDRIES U.S. INC.
To: GLOBALFOUNDRIES INC.
Reel/Frame 036779/0001 →
Security Agreement
Nov 29, 2018
From: GLOBALFOUNDRIES INC.
To: WILMINGTON TRUST, NATIONAL ASSOCIATION
Reel/Frame 049490/0001 →
Assignment of Assignor's Interest
Nov 19, 2020
From: GLOBALFOUNDRIES INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 054482/0862 →
Release of Security Interest
Nov 19, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054479/0842 →
Release of Security Interest
Nov 20, 2020
From: WILMINGTON TRUST, NATIONAL ASSOCIATION
To: GLOBALFOUNDRIES INC.
Reel/Frame 054636/0001 →