Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals
View Patent ↗A semiconductor memory module includes a plurality of semiconductor memory chips and bus signal lines that supply an incoming clock signal and incoming command and address signals to the semiconductor memory chips. A clock signal regeneration circuit and a register circuit are arranged on the semiconductor memory module in a common chip packing connected to the bus signal lines. The clock signal regeneration circuit and the register circuit respectively condition the incoming clock signal and temporarily store the incoming command and address signals, respectively multiply the conditioned clock signal and the temporarily stored command and address signals by a factor of 1:X, and respectively supply to the semiconductor memory chips the conditioned clock signal and the temporarily stored command and address signals.
1. A memory module, comprising:
a plurality of memory chips arranged on the memory module;
a plurality of bus signal lines operable to supply an incoming clock signal and incoming command and address signals to at least the memory chips;
a clock signal regeneration circuit configured to generate a plurality of copies of the incoming clock signal and to supply the copies of the incoming clock signal to the memory chips, the copies of the incoming clock signal having a same frequency as the incoming clock signal; and
a register circuit arrange on the memory module in a common chip packing with the clock regeneration circuit and configured to receive one of the copies of the incoming clock signal from the clock regeneration circuit, the register circuit being further configured to temporarily store the incoming command and address signals and to generate a plurality of copies of the incoming command and address signals and supply the copies of the incoming command and address signals to the memory chips, the copies of the incoming command and address signals having a same frequency as the incoming command and address signals.
2. The memory module according to claim 1 , wherein the clock signal regeneration circuit comprises a phase locked loop (PLL) circuit.
3. The memory module according to claim 1 , wherein the incoming clock signal and the copies of the incoming clock signal are each supplied via differential clock signal lines.
4. The memory module according to claim 1 , wherein the clock signal regeneration circuit and the register circuit are arranged as separate partial chips in the common chip packing.
5. The memory module according to claim 1 , wherein the clock signal regeneration circuit and the register circuit are integrated on a common chip in the common chip packing.
6. The memory module according to claim 1 , wherein the common chip packing is arranged essentially at a central position on the memory module.
7. The memory module according to claim 1 , wherein the bus signal lines of the command and address signals comprise a hybrid-T bus structure.
8. The memory module according to claim 1 , wherein the bus signal lines of the command and address signals comprise a fly-by bus structure.
9. The memory module according to claim 1 , wherein the clock signal regeneration circuit and the register circuit respectively generate two copies of the clock signal and the command and address signals for distribution to the memory chips.
10. The memory module according to claim 1 , wherein the memory module comprises an RDIMM module.
11. The memory module according to claim 1 , wherein the memory chips comprise DDR-DRAM memories.
12. An integrated circuit, comprising:
a clock signal regeneration circuit configured to generate a plurality of copies of a clock signal, wherein the copies of the clock signal have a same frequency as the clock signal; and
a register circuit arranged in a common chip packing with the clock signal regeneration circuit and configured to temporarily store incoming command and address signals and to generate a plurality of copies of the incoming command and address signals, wherein the copies of the incoming command and address signals have a same frequency as the incoming command and address signals, and
wherein the clock signal regeneration circuit supplies one of the copies of the clock signal to the register circuit.
13. The integrated circuit according to claim 12 , wherein the clock signal regeneration circuit comprises a phase locked loop (PLL) circuit.
14. The integrated circuit according to claim 13 , wherein the clock signal regeneration circuit supplies the clock signal as a differential clock signals on differential clock signal lines.
15. The integrated circuit according to claim 14 , wherein the clock signal regeneration circuit and the register circuit are arranged as separate partial chips in the common chip packing.
16. The integrated circuit according to claim 14 , wherein the clock signal regeneration circuit and the register circuit are integrated on a common chip in the common chip packing.
17. The integrated circuit according to claim 12 , wherein the clock signal regeneration circuit and the register circuit respectively generate two copies of the clock signal and the command and address signals for distribution external to the common chip packing.