Patent Assignment
Reel/Frame 023806/0001
Assignment of Assignor's Interest
Recorded: 2010-01-14
Pages: 392
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties
(249)
Multiple Chip Semiconductor Arrangement Having Electrical Components in Separating Regions
Mtj Stack with Crystallization Inhibiting Layer
Standby Current Reduction Over a Process Window with a Trimmable Well Bias
Digital Duty Cycle Corrector
Circuit and Method for Adjusting Threshold Drift Over Temperature in a Cmos Receiver
Alignment of Mtj Stack to Conductive Lines in the Absence of Topography
Scanning Tip Orientation Adjustment Method for Atomic Force Microscopy
Deep Alignment Marks on Edge Chips for Subsequent Alignment of Opaque Layers
Semiconductor Memory Device Comprising Memory Cells with Floating Gate Electrode and Method of Production
Circuit Board and Method for Producing a Circuit Board
Method for Testing the Serviceability of Bit Lines in a Dram Memory Device
Semiconductor Chip with Flexible Contacts at a Face
Method for producing a stack of chips, a stack of chips and method for producing a chip for a multi-chip stack
Application:
10/938,847 →
Publication:
US 2006/0057773
Transistor, Memory Cell Array and Method of Manufacturing a Transistor
Charge-Trapping Semiconductor Memory Device
Method and Apparatus for Characterizing a Recess Located on a Surface of a Substrate
Non-Volatile Semiconductor Memory Device
Charge-Trapping Memory Cell and Charge-Trapping Memory Device
Resistive Memory Element
Memory Device, Memory Controller and Memory System Having Bidirectional Clock Lines
Memory System with Two Clock Lines and a Memory Device
Flexible Blender
Gate Layer Diode Method and Apparatus
Measuring Flare in Semiconductor Lithography
Combined Receiver and Latch
Dqs for Data from a Memory Array
Simulating a Floating Wordline Condition in a Memory Device, and Related Techniques
Method and Apparatus Compensating for Frequency Drift in a Delay Locked Loop
Semiconductor Memory Having Tri-State Driver Device
Circuit Having Delay Locked Loop for Correcting Off Chip Driver Duty Distortion
Variable Delay Line Using Two Blender Delays
Method for Determining an Optimal Absorber Stack Geometry of a Lithographic Reflection Mask
Semiconductor Device and Method of Producing a Semiconductor Device
Apparatus and Method for Making Ground Connection
Duty Distortion Detector
Semiconductor Memory System and Method for the Transfer of Write and Read Data Signals in a Semiconductor Memory System
Memory Access Using Multiple Sets of Address/Data Lines
Sense Amplifier Bitline Boost Circuit
Method for Full Wafer Contact Probing, Wafer Design and Probe Card Device with Reduced Probe Contacts
Flexible Internal Address Counting Method and Apparatus
Twin-Cell Bit Line Sensing Configuration
Random Access Memory Having Fast Column Access
Esd Protection Apparatus for an Electrical Device
Energy Adjusted Write Pulses in Phase-Change Memories
Multi-Pulse Reset Write Scheme for Phase-Change Memories
Patent:
7,031,181 →
Application:
10/995,644 →
Polyelectrolyte Dispensing Polishing Pad
Transistor Array for Semiconductor Memory Devices and Method for Fabricating a Vertical Channel Transistor Array
Circuit and Method for Transmitting a Signal
Non-Volatile Semiconductor Memory
Charge-Trapping Memory Cell and Method for Production
Memory Module with a Clock Signal Regeneration Circuit and a Register Circuit for Temporarily Storing the Incoming Command and Address Signals
Memory Cell Array
Memory Device and Method of Manufacturing a Memory Device
Patent:
7,034,408 →
Application:
11/005,045 →
Method for Production of Charge-Trapping Memory Devices
Patent:
7,026,220 →
Application:
11/006,484 →
Integrated Dram Memory Device
Memory Rank Decoder for a Multi-Rank Dual Inline Memory Module (Dimm)
Stacked Dram Memory Chip for a Dual Inline Memory Module (Dimm)
Method for Fabricating Bottom Electrodes of Stacked Capacitor Memory Cells and Method for Cleaning and Drying a Semiconductor Wafer
Method for Fabricating Bottom Electrodes of Stacked Capacitor Memory Cells
Patent:
7,018,893 →
Application:
11/011,039 →
6F2 Access Transistor Arrangement and Semiconductor Memory Device
Method to Improve Current and Slew Rate Ratio of Off-Chip Drivers
Memory Circuit Receivers Activated by Enable Circuit
Memory Having Test Circuit
Charge-Trapping Memory Device and Method of Production
Memory Access Using Multiple Activated Memory Cell Rows
Delay Locked Loop Using Synchronous Mirror Delay
Memory Having Internal Column Counter for Compression Test Mode
Opto-Electronic Memory Element on the Basis of Organic Metalloporphyrin Molecules
Memory with Selectable Single Cell or Twin Cell Configuration
High Dielectric Constant Materials
Duty Cycle Corrector
Duty Cycle Detector with First, Second, and Third Values
Semiconductor Device
Internal Reference Voltage Generation for Integrated Circuit Testing
Storage Capacitor and Method of Manufacturing a Storage Capacitor
Semiconductor Device and a Method for Fabricating a Semiconductor Device
Patent:
7,026,547 →
Application:
11/040,176 →
Integrated Circuit Including a Memory Having Low Initial Latency
Method of Treating a Structured Surface
Method for Producing a Dielectric Material on a Semiconductor Device and Semiconductor Device
Test Data Topology Write to Memory Using Latched Sense Amplifier Data and Row Address Scrambling
Memory Device Having Components for Transmitting and Receiving Signals Synchronously
Duty Cycle Corrector
Pillar phase change memory cell
Application:
11/048,186 →
Publication:
US 2006/0169968
Methods and Apparatus for Implementing a Power Down in a Memory Device
Method for Interconnecting Semiconductor Components with Substrates and Contact Means
Dissociated Fabrication of Packages and Chips of Integrated Circuits
Integrated Circuit Having a Memory Including a Low-K Dielectric Material for Thermal Isolation
Enhanced Megasonic Based Clean Using an Alternative Cleaning Chemistry
Method and Apparatus for Semiconductor Testing Utilizing Dies with Integrated Circuit
Charge-Trapping Memory Device and Method for Production
Random Access Memory Including Selective Activation of Select Line
Method and System for Fabricating Free-Standing Nanostructures
Patent:
7,008,853 →
Application:
11/066,320 →
Chip Stack Employing a Flex Circuit
Semiconductor Device and Method of Operating a Semiconductor Device
Data Strobe Synchronization for Dram Devices
Memory Device Having Off-Chip Driver Enable Circuit and Method for Reducing Delays During Read Operations
Semiconductor Memory
Memory with Data Latching Circuit Including a Selector
Power Saving Refresh Scheme for Drams with Segmented Word Line Architecture
Stacked Die Package
Test Mode for Detecting a Floating Word Line
Circuit Including a Deskew Circuit for Asymmetrically Delaying Rising and Falling Edges
Methods and Apparatus for Implementing Standby Mode in a Random Access Memory
Memory Device
Integrated Semiconductor Memory Device for Synchronizing a Signal with a Clock Signal
Technique to Read Special Mode Register
Input Circuit Having Updated Output Signal Synchronized to Clock Signal
Patent:
7,123,524 →
Application:
11/128,688 →
Method for Setting a Second Rank Address from a First Rank Address in a Memory Module
Transistor Arrangement in Monocrystalline Substrate Having Stress Exerting Insulators
Flexible Contact-Connection Device
Redistribution Layer with Microstrips
Charge-Trapping Memory Device
Coating Process for Patterned Substrate Surfaces
Method for Fabricating a Shadow Mask in a Trench of a Microelectronic or Micromechanical Structure
Substrate-Based Housing Component with a Semiconductor Chip
Parallel Data Path Architecture
Reflection Mask, Use of the Reflection Mask and Method for Fabricating the Reflection Mask
Method for Fabricating Field-Effect Transistor Structures with Gate Electrodes with a Metal Layer
Semiconductor Device with Semiconductor Components Connected to One Another
Process for Producing a Mask on a Substrate
Temperature Dependent Self-Refresh Module for a Memory Device
Process for Producing a Layer Arrangement, and Layer Arrangement for Use as a Dual-Gate Field-Effect Transistor
Method of Producing a Structure on the Surface of a Substrate
Method for Mounting a Chip on a Base and Arrangement Produced by This Method
Method for Connection of an Integrated Circuit to a Substrate, and a Corresponding Circuit Arrangement
Method for Fabricating Memory Cells for a Memory Device
Phase Change Memory Device with Thermal Insulating Layers
Integrated Semiconductor Memory with Redundant Memory Cells
Fabrication Method for a Trench Capacitor Having an Insulation Collar
Method and Arrangement for Generating an Output Clock Signal with an Adjustable Phase Relation from a Plurality of Input Clock Signals
Device for Setting a Clock Delay
Method and Device for Generating a Clock Signal Using a Phase Difference Signal and a Feedback Signal
Method and Apparatus for the Depth-Resolved Characterization of a Layer of a Carrier
Semiconductor Component with a Mos Transistor
Differential Chip Performance Within a Multi-Chip Package
Method for Testing a Memory Device and Memory Device for Carrying Out the Method
Method for Fabricating a Trench Capacitor with an Insulation Collar and Corresponding Trench Capacitor
Semiconductor Memory and Method for Fabricating the Semiconductor Memory
Fuse Resistance Read-Out Circuit
Semiconductor Apparatus Having Stacked Semiconductor Components
Memory Module Having Memory Chips Protected from Excessive Heat
Method for Testing an Integrated Semiconductor Memory
Reactive Sputtering Process for Optimizing the Thermal Stability of Thin Chalcogenide Layers
Dqs Signaling in Ddr-Iii Memory Systems Without Preamble
Method for Testing an Electric Circuit
Test Method for Determining the Wire Configuration for Circuit Carriers with Components Arranged Thereon
Test System and Method for Testing a Circuit
Method for Fabricating a Trench Isolation Structure Having a High Aspect Ratio
Ferroelectric Memory Arrangement
Integrated Semiconductor Memory with Clock Generation
Integrated Circuit for Regulating a Voltage Generator
Integrated Semiconductor Memory Comprising at Least One Word Line and Method
Loop-Back Method for Measuring the Interface Timing of Semiconductor Devices with the Aid of Signatures and/or Parity Methods
Fabricating a Memory Cell Array
Dram Cell Pair and Dram Memory Cell Array
Semiconductor Memory
Method for Fabricating a Capacitor
Technique to Suppress Bitline Leakage Current
Integrated Circuit and Method for Reading from Resistance Memory Cells
Integrated Semiconductor Memory
Integrated Semiconductor Memory with Test Circuit
Method and Circuit Arrangements for Adjusting Signal Propagation Times in a Memory System
Circuit and Method for Generating an Output Signal
Nonvolatile Memory Cell and Methods for Operating a Nonvolatile Memory Cell
Prestage for an Off-Chip Driver (Ocd)
Integrated Semiconductor Memory and Method for Operating an Integrated Semiconductor Memory
Method for Reducing the Evaluation Outlay in the Monitoring of Layout Changes for Semiconductor Chips
Method for Producing a Rewiring Printed Circuit Board
Flip-Chip Component
Exposure Device for Immersion Lithography and Method for Monitoring Parameters of an Exposure Device for Immersion Lithography
Sense Amplifier Organization for Twin Cell Memory Devices
Semi-Conductor Component, as Well as a Process for the in-or Output of Test Data
Semi-Conductor Component Test Device with Shift Register, and Semi-Conductor Component Test Procedure
Semi-Conductor Component Test Device, in Particular Data Buffer Component with Semi-Conductor Component Test Device, as Well as Semi-Conductor Component Test Procedure
Semiconductor Component, Arrangement and Method for Characterizing a Tester for Semiconductor Components
Integrated Circuit Including Sub-Lithographic Structures
Integrated Semiconductor Memory Device Including Sense Amplifiers
Driver Circuit with Reduced Jitter Between Circuit Domains
Integrated Semiconductor Memory Device
Inputting and Outputting Operating Parameters for an Integrated Semiconductor Memory Device
Integrated Semiconductor Memory Device
Reversible Oxidation Protection of Microcomponents
Method of Making an Integrated Circuit, Including Forming a Contact
Methods for Repairing and for Operating a Memory Component
Method for Producing a Semiconductor Structure
Nonvolatile Memory Cell Arrangement
Output Driver Circuit and a Method of Transmitting an Electrical Signal via an Output Driver Circuit
Method for Transmission and Reception of a Data Signal on a Line Pair, as Well as a Transmission and Reception Circuit for This Purpose
Manufacturing Method with Self-Aligned Arrangement of Solid Body Electrolyte Memory Cells of Minimum Structure Size
Memory Circuit and Method for Reading Out a Memory Datum from Such a Memory Circuit
Method for Testing Semiconductor Chips by Means of Bit Masks
Method for Testing Semiconductor Chips Using Register Sets
Semiconductor Memory System with a Variable and Settable Preamble
Method and System for Carrying Out a Process on an Integrated Circuit
Hybrid silicon-molecular memory cell with high storage density
Application:
11/289,784 →
Publication:
US 2006/0151780
Insertable Calibration Device
Input Circuit for an Integrated Circuit
Semiconductor wafer with a test structure, and method
Application:
11/293,031 →
Publication:
US 2006/0138411
Method and Circuit for Reading a Dynamic Memory Circuit
Method for Activating a Plurality of Word Lines in a Refresh Cycle, and Electronic Memory Device
Voltage Supply Circuit, in Particular for a Dram Memory Circuit, as Well as a Method for Controlling a Supply Source
Mask and exposure device
Application:
11/295,691 →
Publication:
US 2006/0121365
Method of Producing a Conductive Layer Including Two Metal Nitrides
Integrated Circuit
Method of Producing a Microelectronic Electrode Structure, and Microelectronic Electrode Structure
Memory Component and Addressing of Memory Cells
Memory Component Having a Novel Arrangement of the Bit Lines
Semiconductor Wafer with Test Structure
Chip Component and Method for Producing a Chip Component
Driver Circuit for Binary Signals
Means of Mounting for Electronic Components, Arrangement and Procedure
Integrated Charge Pump
Semiconductor Memory Device, System with Semiconductor Memory Device, and Method for Operating a Semiconductor Memory Device
Integrated Semiconductor Memory Device with Adaptation of the Evaluation Characteristic of Sense Amplifiers
Integrated Semiconductor Memory Device with Test Circuit for Sense Amplifier
Integrated Circuit Including a Memory Apparatus and Production Method
Integrated Semiconductor Memory and Method for Operating a Semiconductor Memory
Synchronous Parallel/Serial Converter
Integrated Memory Circuit and Method for Repairing a Single Bit Error
Non-Volatile Memory Cell for Storage of a Data Item in an Integrated Circuit
Method for correcting the optical proximity effect
Application:
11/336,092 →
Publication:
US 2006/0195808
Semiconductor Product Having a Semiconductor Substrate and a Test Structure and Method
Substrate for an Fbga Semiconductor Component
Apparatus for Projecting a Pattern into an Image Plane
Memory Device and Method for Testing Memory Devices with Repairable Redundancy
Integrated Semiconductor Memory
Test System for Testing Integrated Circuits and a Method for Configuring a Test System
Integrated Semiconductor Memory with Clock-Synchronous Access Control
Integrated Semiconductor Memory with Adjustable Internal Voltage
Control Unit for Deactivating and Activating the Control Signals
Test Apparatus and Method for Testing a Circuit Unit
Receiver Circuit
Charge Trapping Semiconductor Memory Element with Improved Trapping Dielectric
Dll Circuit for Providing an Adjustable Phase Relationship with Respect to a Periodic Input Signal
Miniaturized Detection Coil Former for Nmr Spectroscopy
Circuit for Producing a Data Bit Inversion Flag
Field Effect Transistor with Gate Spacer Structure and Low-Resistance Channel Coupling
Integrated Semiconductor Memory Having Sense Amplifiers Selectively Activated at Different Timing
Lithography mask and methods for producing a lithography mask
Application:
11/366,027 →
Publication:
US 2006/0210887
Buffer Component for a Memory Module, and a Memory Module and a Memory System Having Such Buffer Component
Circuit for Data Bit Inversion
Contacting Device, Testing Method and Corresponding Production Method
Semiconductor Memory Component and Method for Testing Semiconductor Memory Components Having a Restricted Memory Area (Partial Good Memories)
Semiconductor Memory Component and Method for Testing Semiconductor Memory Components
Memory Module for Point-to-Point Data Interchange
Application:
11/377,473 →
Publication:
US 2007/0033351
Method and Device for Transmission of Adjustment Information for Data Interface Drivers for a Ram Module
Device in a Memory Circuit for Definition of Waiting Times
Semiconductor Memory and Method for Adapting the Phase Relationship Between a Clock Signal and Strobe Signal During the Acceptance of Write Data to Be Transmitted
Nonvolatile Memory Cell
Related Assignments
(3)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Oct 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036888/0745 →
Assignment of Assignor's Interest
Oct 21, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036908/0923 →