Method for connection of an integrated circuit to a substrate, and a corresponding circuit arrangement
View Patent ↗The present invention provides a method for connection of an integrated circuit ( 1 ), in particular of a chip, a wafer or a hybrid, to a substrate ( 10 ), which has the following steps: provision of an elastic intermediate layer ( 5 ) on the integrated circuit ( 1 ) and/or the substrate ( 10 ); structuring of the elastic layer ( 5 ) in raised areas ( 5 a ) and recessed areas ( 5 b ); and connection of the substrate ( 10 ) and of the integrated circuit ( 1 ) via the structured elastic intermediate layer ( 5 ). The invention likewise provides a corresponding circuit arrangement.
1. A method for connection of an integrated circuit, in particular of a chip, a wafer or a hybrid, to a substrate, which has the following steps:
(a) providing an elastic intermediate layer on the integrated circuit and/or the substrate;
(b) structuring the elastic layer in raised areas and recessed areas wherein the structuring of the elastic layer comprises at least two concentric circular reliefs around the same center of the integrated circuit; and
(c) connecting the substrate and the integrated circuit via the structured elastic intermediate layer,
wherein a metallization structure in a form of at least one strip contacts the circular reliefs and is oriented at right angles to the circular reliefs.
2. The method according to claim 1 , wherein the connection is made directly.
3. The method according to claim 1 , wherein the connection is made indirectly by provision of an intermediate adhesive layer.
4. The method according to claim 1 , wherein the raised and/or recessed areas are structured such that they have a variable width.
5. The method according to claim 1 , wherein the structuring is carried out photolithographically.
6. The method according to claim 1 , wherein the elastic intermediate layer is provided and structured only on the integrated circuit or only on the substrate, and a thermally conductive layer is provided above the structured elastic intermediate layer, but does not fill the recessed areas.
7. The method according to claim 1 , wherein the elastic intermediate layer is provided and structured only on the integrated circuit or only on the substrate, and the recessed areas are filled with a thermally conductive layer.