Patent Assignment
Reel/Frame 036888/0745
Assignment of Assignor's Interest
Recorded: 2015-10-19
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(219)
Charge-Trapping Memory Device Including High Permittivity Strips
Dual-Purpose Shift Register
Chip to Chip Interface for Encoding Data and Clock Signals
Chip to Chip Interface
Method for Removing a Resist Mask with High Selectivity to a Carbon Hard Mask Used for Semiconductor Structuring
Methods for Forming Vertical Gate Transistors Providing Improved Isolation and Alignment of Vertical Gate Contacts
Method of and System for Analyzing Cells of a Memory Device
Post Metal Chemical Mechanical Polishing Dry Cleaning
Integrated Circuit with Re-Route Layer and Stacked Die Assembly
Method for Producing Semiconductor Memory Devices and Integrated Memory Device
Clock Stop Detector
Temperature Sensor Scheme
Clock Distortion Detector Using a Synchronous Mirror Delay Circuit
Switching Device for Configurable Interconnect and Method for Preparing the Same
Charge-Trapping Memory Cell Array and Method for Production
Circuit Board for Connecting an Integrated Circuit to a Support and Ic Bga Package Using Same
Multichip Package with Clock Frequency Adjustment
Threshold Voltage Detector for Process Effect Compensation
Memory with Adjustable Access Time
Circuit Module
Circuit Board
Switching Device for Reconfigurable Interconnect and Method for Making the Same
Flash Memory Cell, Flash Memory Device and Manufacturing Method Thereof
Method of Optimizing the Timing Between Signals
Process Monitoring by Comparing Delays Proportional to Test Voltages and Reference Voltages
Duty Cycle Correction
Method for Localization and Generation of Short Critical Sequence
Multiple Chip Semiconductor Arrangement Having Electrical Components in Separating Regions
Chip to Chip Interface
Method for Initializing the Computation of a Quasi-Periodic Steady State of a Multi-Tone System
Comparator and Method for Amplifying an Input Signal
Comparator Using Differential Amplifier with Reduced Current Consumption
Input Return Path Based on Vddq/Vssq
Mtj Stack with Crystallization Inhibiting Layer
Standby Current Reduction Over a Process Window with a Trimmable Well Bias
Wafer Probecard Interface
Test Circuitry Wafer
Process for Fabrication of a Ferrocapacitor
Digital Duty Cycle Corrector
Circuit and Method for Adjusting Threshold Drift Over Temperature in a Cmos Receiver
Method for Forming a Capacitor for an Integrated Circuit and Integrated Circuit
Alignment of Mtj Stack to Conductive Lines in the Absence of Topography
Deep Alignment Marks on Edge Chips for Subsequent Alignment of Opaque Layers
Method for Testing the Serviceability of Bit Lines in a Dram Memory Device
Current Sense Amplifier
Method and Apparatus for Characterizing a Recess Located on a Surface of a Substrate
Arrangement and Process for Protecting Fuses/Anti-Fuses
Process for Fabricating a Semiconductor Device Having Deep Trench Structures
Memory Device and Method Using a Sense Amplifier as a Cache
Method for Dynamically Monitoring a Reticle
Test Device for Wafer Testing Digital Semiconductor Circuits
Method for Fabricating a Semiconductor Structure
Method for Improving the Read Signal in a Memory Having Passive Memory Elements
Integrated Circuit for Storing Operating Parameters
Method and Apparatus for the Characterization of a Depth Structure in a Substrate
Socket and/or Adapter Device, and an Apparatus and Process for Loading a Socket and/or Adapter Device with a Corresponding Semi-Conductor Component
Arrangement for Determining a Temperature Loading of an Integrated Circuit and Method
Loading a Socket and/or Adapter Device with a Semiconductor Component
Test System and Test Structure for Testing an Integrated Circuit and an Integrated Circuit Having a Test Structure
Method for Testing an Integrated Semiconductor Memory, and Integrated Semiconductor Memory
Semiconductor Memory Circuit and Method for Operating the Same in a Standby Mode
Integrated Circuit and Method for Generating a Ready Signal
Receiver Circuit Arrangement Having an Inverter Circuit
Method and Apparatus for Testing Circuit Units to Be Tested with Different Test Mode Data Sets
Fabrication Method for a Semiconductor Structure and Corresponding Semiconductor Structure
Device to Be Used in the Synchronization of Clock Pulses, as Well as a Clock Pulse Synchronization Process
Voltage Booster Device for Semi-Conductor Components
Polymers Based on Cinnamic Acid as a Bottom Antireflective Coating for 157 Nm Photolithography
Memory Cell, Method for the Production Thereof and Use of a Composition Therefor
Voltage Regulation System
Method for Fabricating Metallic Interconnects on Electronic Components
Capacitor with a Dielectric Including a Self-Organized Monolayer of an Organic Compound
Integrated Semiconductor Memory with Temperature-Dependent Voltage Generation
Integrated Semiconductor Memory with Redundant Memory Cells Replaceable for Either True or Complementary Defective Memory Cells
Method for Expanding a Trench in a Semiconductor Structure
Method for Fabricating a Memory Cell
Charge Trapping Memory Cell and Fabrication Method
Memory Device Electrode with a Surface Structure
Process for Producing a Mask
Method and Apparatus for Determination of the Depth of Depressions Which Are Formed in a Mount Substrate
Integrated Semiconductor Memory and Method for Electrically Stressing an Integrated Semiconductor Memory
Fabrication Method for Semiconductor Structure in a Substrate, the Semiconductor Structure Having at Least Two Regions That Are to Be Patterned Differently
Method for Through-Plating Field Effect Transistors with a Self-Assembled Monolayer of an Organic Compound as Gate Dielectric
Contact Plate for Use in Standardizing Tester Channels of a Tester System and a Standardization System Having Such a Contact Plate
Method for Fabricating a Field Effect Transistor
Semiconductor Component Having at Least One Organic Semiconductor Layer and Method for Fabricating the Same
Integrated Semiconductor Memory with Sense Amplifier
Circuit Arrangement for Latency Regulation
Method and Apparatus for Determining Local Variation of the Reflection or Transmission Behavior Over a Mask Surface
Method for Fabricating a Semiconductor Structure
Integrated Semiconductor Memory Device and Method for Operating an Integrated Semiconductor Memory Device
Method for Operating an Electrical Writable and Erasable Memory Cell and a Memory Device for Electrical Memories
Integratable, Controllable Delay Device, Use of a Delay Device, as Well as an Integratable Multiplexer for Use in a Delay Device
Method for Fabricating a Stacked Capacitor Array Having a Regular Arrangement of a Plurality of Stacked Capacitors
Field Effect Semiconductor Switch and Method for Fabricating It
Monitoring Device for Monitoring Internal Signals During Initialization of an Electronic Circuit
Computer-Supported, Automated Method for the Verification of Analog Circuits
Integrated Circuit
Input Circuit for an Electronic Circuit and a Method for Controlling the Reading-in of a Data Signal
Parallel-Serial Converter
Semiconductor Component with Internal Heating
Integrated Module Having a Plurality of Separate Substrates
Integrated Circuit for Determining a Voltage
Integrated Circuit
Write/Delete Process for Resistive Switching Memory Components
Reducing Current Consumption for Input Circuit of an Electronic Circuit
Method for Testing an Integrated Semiconductor Memory with a Shortened Reading Time
Method and Apparatus for Measuring a Surface Profile of a Sample
System for Determining a Reference Level and Evaluating a Signal on the Basis of the Reference Level
Fabrication Method for a Semiconductor Structure
Integrated Semiconductor Circuit and Method for Testing the Same
Electronic Memory Apparatus, and Method for Deactivating Redundant Bit Lines or Word Lines
Masks for Lithographic Imagings and Methods for Fabricating the Same
Integrated Circuit Including Memory Cell for Storing an Information Item and Method
Trench and a Trench Capacitor and Method for Forming the Same
Memory Circuit and Method for Providing an Item of Information for a Prescribed Period of Time
Method for the Formation of a Structure Size Measured Value
Stacked Capacitor Array and Fabrication Method for a Stacked Capacitor Array
Method for Testing a Memory Chip and Test Arrangement
Method and Circuit Arrangement for Controlling Write Access to a Semiconductor Memory
Method for Production of Trench Dram Cells and a Trench Dram Cell Array with Fin Field-Effect Transistors with a Curved Channel (Cfet - Curved Fets)
Method and Circuit Arrangement for Resetting an Integrated Circuit
Dram Memory Cell Arrangement
Method for Testing an Integrated Semiconductor Memory
Integrated Semiconductor Memory
Integrated Circuit for Stabilizing a Voltage
Method for Fabricating Dielectric Mixed Layers and Capacitive Element and Use Thereof
Fabrication Method for a Semiconductor Structure Having Integrated Capacitors
Backwards-Compatible Memory Module
Semiconductor Chip with Metallization Levels, and a Method for Formation of Interconnect Structures
Input Circuit for Receiving an Input Signal, and a Method for Adjusting an Operating Point of an Input Circuit
Transistor Arrangement in Monocrystalline Substrate Having Stress Exerting Insulators
Method for Activating and Deactivating Electronic Circuit Units and Circuit Arrangement for Carrying Out the Method
Thin Film Field Effect Transistor with Gate Dielectric Made of Organic Material and Method for Fabricating the Same
Memory Circuit, and Method for Reading Out Data Contained in the Memory Circuit Using Shared Command Signals
Integrated Circuit
Read Latency Control Circuit
Flexible Contact-Connection Device
Electronic Circuit Apparatus and Method for Stacking Electronic Circuit Units
Integrated Circuit
Integrated Semiconductor Memory Comprising at Least One Word Line and Comprising a Multiplicity of Memory Cells
Integrated Semiconductor Memory
Memory Circuit Comprising Redundant Memory Areas
Test Apparatus and Method for Testing Circuit Units to Be Tested
Coating Process for Patterned Substrate Surfaces
Method for Connecting an Integrated Circuit to a Substrate and Corresponding Circuit Arrangement
Method for Producing a Package for an Electronic Circuit and a Substrate for a Package
Memory Device with Multistage Sense Amplifier
Method for Fabricating a Shadow Mask in a Trench of a Microelectronic or Micromechanical Structure
Substrate-Based Housing Component with a Semiconductor Chip
Reflection Mask, Use of the Reflection Mask and Method for Fabricating the Reflection Mask
Semiconductor Memory Device
Resistive Semiconductor Element Based on a Solid-State Ion Conductor
Method for Determining a Matrix of Transmission Cross Coefficients in an Optical Proximity Correction of Mask Layouts
Method for Fabricating Field-Effect Transistor Structures with Gate Electrodes with a Metal Layer
Device and a Process for the Calibration of a Semiconductor Component Test System
Method for Fabricating a Dram Memory Cell Arrangement Having Fin Field Effect Transistors and Dram Memory Cell
Method for Adapting Structure Dimensions During the Photolithographic Projection of a Pattern of Structure Elements Onto a Semiconductor Wafer
Semiconductor Device with Semiconductor Components Connected to One Another
Process for Producing a Mask on a Substrate
Process for Producing a Layer Arrangement, and Layer Arrangement for Use as a Dual-Gate Field-Effect Transistor
Digital Ram Memory Circuit with an Expanded Command Structure
Method of Producing a Structure on the Surface of a Substrate
Method for Mounting a Chip on a Base and Arrangement Produced by This Method
Method for Connection of an Integrated Circuit to a Substrate, and a Corresponding Circuit Arrangement
Integrated Semiconductor Memory with Redundant Memory Cells
Semiconductor Circuit Device and a System for Testing a Semiconductor Apparatus
Method for Correcting Structure-Size-Dependent Positioning Errors in Photolithography
Integrated Semiconductor Memory
Method for Correcting Layout Errors
Method for Production of a Standard Cell Arrangement, and Apparatus for Carrying Out the Method
Method and Arrangement for Generating an Output Clock Signal with an Adjustable Phase Relation from a Plurality of Input Clock Signals
Device for Setting a Clock Delay
Method and Device for Generating a Clock Signal Using a Phase Difference Signal and a Feedback Signal
Semiconductor Component with a Mos Transistor
Method for Testing a Memory Device and Memory Device for Carrying Out the Method
Semiconductor Memory and Method for Fabricating the Semiconductor Memory
Integrated Memory Arrangement Based on Resistive Memory Cells and Production Method
Semiconductor and Method for Producing a Semiconductor
Semiconductor Apparatus Having Stacked Semiconductor Components
Clock Signal Synchronizing Device, and Clock Signal Synchronizing Method
Reactive Sputtering Process for Optimizing the Thermal Stability of Thin Chalcogenide Layers
Dqs Signaling in Ddr-Iii Memory Systems Without Preamble
Method for Testing an Electric Circuit
Test Method for Determining the Wire Configuration for Circuit Carriers with Components Arranged Thereon
Test System and Method for Testing a Circuit
Method for Fabricating a Trench Isolation Structure Having a High Aspect Ratio
Integrated Semiconductor Memory with Clock Generation
Integrated Circuit for Regulating a Voltage Generator
Integrated Semiconductor Memory Comprising at Least One Word Line and Method
Loop-Back Method for Measuring the Interface Timing of Semiconductor Devices with the Aid of Signatures and/or Parity Methods
Fabricating a Memory Cell Array
Dram Cell Pair and Dram Memory Cell Array
Semiconductor Memory
Integrated Circuit and Method for Reading from Resistance Memory Cells
Self Test for the Phase Angle of the Data Read Clock Signal Dqs
Method and Circuit Arrangements for Adjusting Signal Propagation Times in a Memory System
Method for Reducing the Evaluation Outlay in the Monitoring of Layout Changes for Semiconductor Chips
Exposure Device for Immersion Lithography and Method for Monitoring Parameters of an Exposure Device for Immersion Lithography
Charge-Trapping Memory Device and Methods for Operating and Manufacturing the Cell
Memory Circuit and Method for Reading Out a Memory Datum from Such a Memory Circuit
Method and Circuit for Reading a Dynamic Memory Circuit
Duty Cycle Correction
Test System for Testing Integrated Circuits and a Method for Configuring a Test System
Multichip Package with Clock Frequency Adjustment
Method for Producing Semiconductor Memory Devices and Integrated Memory Device
Standby Current Reduction Over a Process Window with a Trimmable Well Bias
Clock Stop Detector
Intergrated Circuit for Programming Resistive Memory Cells
Silanized Carbon Nanotubes and Method for the Production Thereof
Method for Operating an Electrical Writable and Erasable Memory Cell and a Memory Device for Electrical Memories
Mram Memory Cell Having a Weak Intrinsic Anisotropic Storage Layer and Method of Producing the Same
Semiconductor Memory Device
Integrated Circuit, Method of Operating an Integrated Circuit, Method of Manufacturing an Integrated Circuit, Memory Module, Stackable Memory Module
Mram Memory Cell Having a Weak Intrinsic Anisotropic Storage Layer and Method of Producing the Same
Field-Effect Transistor Structures with Gate Electrodes with a Metal Layer
Post Metal Chemical Mechanical Polishing Dry Cleaning
Method for Producing a Structure on the Surface of a Substrate
Integrated Circuit with Re-Route Layer and Stacked Die Assembly
Related Assignments
(4)
Other recorded transfers of the patents in this record — the chain of ownership.
Assignment of Assignor's Interest
Jan 13, 2010
From: INFINEON TECHNOLOGIES RICHMOND, LP
To: QIMONDA AG
Reel/Frame 023792/0001 →
Assignment of Assignor's Interest
Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
Assignment of Assignor's Interest
May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
Assignment of Assignor's Interest
Feb 12, 2020
From: POLARIS INNOVATIONS LIMITED
To: CHANGXIN MEMORY TECHNOLOGIES, INC
Reel/Frame 051917/0581 →