IP Library Granted Patent US 7,193,426
Granted Patent B2
US 7,193,426 · App. 11/013,873 · Granted Mar 20, 2007

Test system and test structure for testing an integrated circuit and an integrated circuit having a test structure

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Quick Facts
Patent No.
US 7,193,426
App. No.
11/013,873
Granted
Mar 20, 2007
Kind
B2
Abstract

One embodiment of the invention relates to a test structure for testing an integrated circuit with a tester unit that has one or more connecting lines to connect the integrated circuit, wherein a test signal and/or a supply voltage is applied to the integrated circuit for the purposes of testing, and an interference unit connected to at least one of the connecting lines which applies an interference signal to the connecting line to reduce the quality of the test signal and/or the quality of the supply voltage.

Claims (16)

1. An integrated circuit, comprising:

a functional circuit having one or more connecting lines connectable to at least one of a test signal, an internal supply voltage and an external supply voltage;

an interference unit for generating an interference signal during a test operation, the interference unit disposed in connection to at least one of the connecting lines and configured to modify at least one of the test signal, the internal supply voltage and the external supply voltage on the respectively connected connecting lines based on the interference signal;

wherein the one or more connecting lines include at least one of an internal voltage supply line of the integrated circuit and an external voltage supply line; and

wherein the interference unit is connected to an internal voltage source which regulates internal supply voltage in accordance with a reference voltage, wherein the interference signal is superposed onto the reference voltage.

2. An integrated circuit, comprising:

a functional circuit having one or more connecting lines connectable to at least one of a test signal, an internal supply voltage and an external supply voltage, wherein the one or more connecting lines include at least one of an internal supply voltage line of the integrated circuit and an external supply voltage line; and

an interference unit for generating an interference signal during a test operation, the interference unit disposed in connection to at least one of the connecting lines and configured to modify at least one of the test signal, the internal supply voltage and the external supply voltage on the respectively connected connecting lines based on the interference signal, wherein the interference unit comprises:

a transistor connected between a fixed potential and one of the internal supply voltage line of the integrated circuit and the external supply voltage line; and

an interference source connected to drive the transistor.

3. The integrated circuit of claim 2 , further comprising:

one or more external terminals connected to the one or more connecting lines, wherein the test signal and the external supply voltage are provided from a tester unit via the external terminals.

4. The integrated circuit of claim 2 , wherein the interference signal is superposed onto a supply voltage to generate the external supply voltage applied to the integrated circuit.

5. The integrated circuit of claim 2 , wherein the interference unit is selectively activated with a test mode signal.

6. A method for testing an integrated circuit, comprising:

applying an interference signal to at least one of an internal supply voltage and an external supply voltage during testing of the integrated circuit with a tester unit in accordance with a test mode, wherein the interference signal reduces at least one of a supply voltage quality of the internal supply voltage and a supply voltage quality of the external supply voltage.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 19, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036888/0745 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2005
From: POCHMUELLER, PETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015852/0479 →