Patent Assignment
Reel/Frame 023853/0001
Assignment of Assignor's Interest
Recorded: 2010-01-15
Pages: 392
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2006-04-25
Assignee
QIMONDA AG
GUSTAV-HEINEMANN-RING 212, MUNICH, 81739, GERMANY
Covered Properties
(249)
Reduced Power Consumption in Integrated Circuits with Fuse Controlled Redundant Circuits
Reference Voltage Detector for Power-on Sequence in a Memory
Reliable Ferro Fuse Cell
Device for Inhibiting Hydrogen Damage in Ferroelectric Capacitor Devices
Random Access Memory Having Driver for Reduced Leakage Current
Memory Device Having Multiple Array Structure for Increased Bandwidth
Memory System with Reduced Refresh Current
Patent:
6,862,238 →
Application:
10/672,244 →
Temperature Sensor Scheme
Method for Producing a Ferroelectric Capacitor That Includes Etching with Hardmasks
Memory Device with a Flexible Reduced Density Option
Random Access Memory with Post-Amble Data Strobe Signal Noise Rejection
System and Method for Automatically-Detecting Soft Errors in Latches of an Integrated Circuit
Echo Clock on Memory System Having Wait Information
Device and a Method for Forming a Ferroelectric Capacitor Device
Device and a Method for Forming a Capacitor Device
Method for Forming Ferrocapacitors and Feram Devices
Voltage Trimming Circuit
Method and Circuit Configuration for Digitizing a Signal in an Input Buffer of a Dram Device
Reference Current Distribution in Mram Devices
Mask and Method for Using the Mask in Lithographic Processing
Method and Circuit Configuration for Multiple Charge Recycling During Refresh Operations in a Dram Device
Patent:
6,847,566 →
Application:
10/692,119 →
Device and Method for Inhibiting Oxidation of Contact Plugs in Ferroelectric Capacitor Devices
Ferroelectric Capacitor Devices and a Method for Compensating for Damage to a Capacitor Caused by Etching
Refresh for Dynamic Cells with Weak Retention
Latch Scheme with Invalid Command Detector
Patent:
6,839,288 →
Application:
10/706,146 →
Ferroelectric Capacitor Devices and Feram Devices
Charge-Trapping Memory Device Including High Permittivity Strips
Method and Circuit Configuration for Refreshing Data in a Semiconductor Memory
Low Rise/Fall Skewed Input Buffer Compensating Process Variation
Dual-Purpose Shift Register
Internal Voltage Generator with Temperature Control
Back-Bias Voltage Generator with Temperature Control
Dual Power Sensing Scheme for a Memory Device
Methods and Apparatus for Active Termination of High-Frequency Signals
Random Access Memory with Optional Inaccessible Memory Cells
Chip to Chip Interface for Encoding Data and Clock Signals
Chip to Chip Interface
Imprint Suppression Circuit Scheme
Method for Removing a Resist Mask with High Selectivity to a Carbon Hard Mask Used for Semiconductor Structuring
Random Access Memory Using Precharge Timers in Test Mode
Method and Apparatus for Controlling Refresh Cycles of a Plural Cycle Refresh Scheme in a Dynamic Memory
Input Buffer Circuit Including Reference Voltage Monitoring Circuit
Oscillator with Temperature Control
Methods for Forming Vertical Gate Transistors Providing Improved Isolation and Alignment of Vertical Gate Contacts
Input Buffer with Differential Amplifier
Patent:
6,891,763 →
Application:
10/744,804 →
Temperature Compensated Delay Signals
Burst Mode Implementation in a Memory Device
Memory device controlled with user-defined commands
Application:
10/748,224 →
Publication:
US 2005/0144372
Memory with Auto Refresh to Designated Banks
Patent:
6,859,407 →
Application:
10/757,275 →
Memory Device with Non-Variable Write Latency
Method for Formation of an Ultra-Thin Film and Semiconductor Device Containing Such a Film
System and Method for Refreshing a Dynamic Memory Device
Patent:
6,914,841 →
Application:
10/768,202 →
Method for Producing Semiconductor Memory Devices and Integrated Memory Device
Clock Stop Detector
Memory Device with Common Row Interface
Temperature Sensor Scheme
Clock Distortion Detector Using a Synchronous Mirror Delay Circuit
Switching Device for Configurable Interconnect and Method for Preparing the Same
Charge-Trapping Memory Cell Array and Method for Production
Circuit Board for Connecting an Integrated Circuit to a Support and Ic Bga Package Using Same
Multichip Package with Clock Frequency Adjustment
Threshold Voltage Detector for Process Effect Compensation
Memory with Adjustable Access Time
Circuit Module
Circuit Board
Switching Device for Reconfigurable Interconnect and Method for Making the Same
Flash Memory Cell, Flash Memory Device and Manufacturing Method Thereof
Method of Optimizing the Timing Between Signals
Process Monitoring by Comparing Delays Proportional to Test Voltages and Reference Voltages
Duty Cycle Correction
Method for Localization and Generation of Short Critical Sequence
Chip to Chip Interface
Method for Initializing the Computation of a Quasi-Periodic Steady State of a Multi-Tone System
Comparator and Method for Amplifying an Input Signal
Comparator Using Differential Amplifier with Reduced Current Consumption
Input Return Path Based on Vddq/Vssq
Wafer Probecard Interface
Test Circuitry Wafer
Process for Fabrication of a Ferrocapacitor
Method for Fabricating a Trench Capacitor with an Insulation Collar Which Is Electrically Connected to a Substrate on One Side via a Buried Contact, in Particular for a Semiconductor Memory Cell
Method for Forming a Capacitor for an Integrated Circuit and Integrated Circuit
Memory Cell with Nanocrystals or Nanodots
Apparatus and Method for Testing Circuit Units to Be Tested
Test Arrangement for Testing Semiconductor Circuit Chips
Semiconductor Memory Module
Fbga Arrangement
Process for Sealing Plasma-Damaged, Porous Low-K Materials
Method for Fabricating a Trench Capacitor Having an Insulation Collar, Which Is Electrically Connected to a Substrate on One Side via a Buried Contact, in Particular for a Semiconductor Memory Cell
Method for Fabricating an Integrated Circuit Device with Through-Plating Elements and Terminal Units
Data Processing Circuit Apparatus Having a Data Transmission Unit of Redundant Design
Method for Testing Circuit Units to Be Tested and Test Apparatus
Circuit Arrangement for Setting a Voltage Supply for a Test Mode of an Integrated Memory
Method for Carrying Out a Double or Multiple Exposure
Signal Test Procedure for Testing Semi-Conductor Components and a Test Apparatus for Testing Semi-Conductor Components
Apparatus for Calibrating the Relative Phase of Two Reception Signals of a Memory Chip
Apparatus for Testing a Memory Module
Nonvolatile Integrated Semiconductor Memory
Alignment Mark for Coarse Alignment and Fine Alignment of a Semiconductor Wafer in an Exposure Tool
Phase Shift Mask
Method for Fabricating Memory Cells and Memory Cell Array
Method for the Characterization of a Film
Method for Producing a Multichip Module and Multichip Module
Charge Trapping Memory Cell
Method for Fabricating Memory Components
Integrated Memory Circuit
Method for Operating a Memory Cell Array
Long Running Test Method for a Circuit Design Analysis
Method for Testing Circuit Units to Be Tested by Means of Majority Decisions and Test Device for Performing the Method
Arrangement and Process for Protecting Fuses/Anti-Fuses
Method for Fabricating a Semiconductor Structure with an Encapsulation of a Filling Which Is Used for Filling Trenches
Wafer Level Packages for Chips with Sawn Edge Protection
Process for Generating a Hard Mask for the Patterning of a Layer
Level Converter
Clock Signal Synchronizing Device, and Clock Signal Synchronizing Method
Trench Capacitor Structure and Process for Applying a Covering Layer and a Mask for Trench Etching Processes in Semiconductor Substrates
Apparatus and Method for Proof of Outgassing Products
Transistor Structure, Memory Cell, Dram, and Method for Fabricating a Transistor Structure in a Semiconductor Substrate
Pseudodynamic Off-Chip Driver Calibration
Memory Cell and Method for Fabricating It
Method for Dynamically Monitoring a Reticle
Method and Imaging Apparatus for Imaging a Structure Onto a Semiconductor Wafer by Means of Immersion Lithography
Input Switching Arrangement for a Semiconductor Circuit and Test Method for Unidirectional Input Drivers in Semiconductor Circuits
Test Device for Wafer Testing Digital Semiconductor Circuits
Method for Improving a Simulation Model of Photolithographic Projection
Method for Fabricating a Semiconductor Structure
Electronic Component with Compliant Elevations Having Electrical Contact Areas and Method for Producing It
Method, computer program, apparatus and system for the selective communication of data sets
Application:
10/999,809 →
Publication:
US 2005/0138062
Method for Improving the Read Signal in a Memory Having Passive Memory Elements
Integrated Circuit for Storing Operating Parameters
Method and Apparatus for the Characterization of a Depth Structure in a Substrate
Socket and/or Adapter Device, and an Apparatus and Process for Loading a Socket and/or Adapter Device with a Corresponding Semi-Conductor Component
Method for Producing an Integrated Memory Module
Circuit
Arrangement for Determining a Temperature Loading of an Integrated Circuit and Method
Loading a Socket and/or Adapter Device with a Semiconductor Component
Test System and Test Structure for Testing an Integrated Circuit and an Integrated Circuit Having a Test Structure
Method for Testing an Integrated Semiconductor Memory, and Integrated Semiconductor Memory
Transistor Structure with a Curved Channel, Memory Cell and Memory Cell Array for Drams, and Methods for Fabricating a Dram
Memory Component with Improved Noise Insensitivity
Semiconductor Memory Circuit and Method for Operating the Same in a Standby Mode
Integrated Circuit and Method for Generating a Ready Signal
Method for Fabricating Contact-Making Connections
Receiver Circuit Arrangement Having an Inverter Circuit
Method and Apparatus for Testing Circuit Units to Be Tested with Different Test Mode Data Sets
Fabrication Method for a Semiconductor Structure and Corresponding Semiconductor Structure
Semiconductor Memory Device with Write Protected Memory Banks
Device to Be Used in the Synchronization of Clock Pulses, as Well as a Clock Pulse Synchronization Process
Voltage Booster Device for Semi-Conductor Components
Polymers Based on Cinnamic Acid as a Bottom Antireflective Coating for 157 Nm Photolithography
Memory Cell, Method for the Production Thereof and Use of a Composition Therefor
Voltage Regulation System
Method for Fabricating Metallic Interconnects on Electronic Components
Capacitor with a Dielectric Including a Self-Organized Monolayer of an Organic Compound
Process for Producing Metallic Interconnects and Contact Surfaces on Electronic Components
Integrated Semiconductor Memory with Temperature-Dependent Voltage Generation
Process for Producing Layer Structures for Signal Distribution
Method for Matching Two Measurement Methods for Measuring Structure Widths on a Substrate
Integrated Semiconductor Memory with Redundant Memory Cells Replaceable for Either True or Complementary Defective Memory Cells
Method for Expanding a Trench in a Semiconductor Structure
Method for Fabricating a Memory Cell
Charge Trapping Memory Cell and Fabrication Method
Dram Memory and Method for Fabricating a Dram Memory Cell
Memory Device Electrode with a Surface Structure
Process for Producing a Mask
Method and Apparatus for Determination of the Depth of Depressions Which Are Formed in a Mount Substrate
Integrated Semiconductor Memory and Method for Electrically Stressing an Integrated Semiconductor Memory
Fabrication Method for Semiconductor Structure in a Substrate, the Semiconductor Structure Having at Least Two Regions That Are to Be Patterned Differently
Method for Through-Plating Field Effect Transistors with a Self-Assembled Monolayer of an Organic Compound as Gate Dielectric
Semiconductor Memory Having a First and Second Sense Amplifier for Sensing a Memory Cell Voltage During a Normal Mode and a Refresh Mode
Method for Smoothing Areas in Structures by Utilizing the Surface Tension
Contact Plate for Use in Standardizing Tester Channels of a Tester System and a Standardization System Having Such a Contact Plate
Method for Fabricating a Field Effect Transistor
Self-assembly organic dielectric layers based on phosphonic acid derivatives
Application:
11/066,617 →
Publication:
US 2005/0189536
Semiconductor Component Having at Least One Organic Semiconductor Layer and Method for Fabricating the Same
Integrated Semiconductor Memory with Sense Amplifier
Circuit Arrangement for Latency Regulation
Method and Apparatus for Determining Local Variation of the Reflection or Transmission Behavior Over a Mask Surface
Method for Fabricating a Semiconductor Structure
Integrated Semiconductor Memory Device and Method for Operating an Integrated Semiconductor Memory Device
Method for Operating an Electrical Writable and Erasable Memory Cell and a Memory Device for Electrical Memories
Method and Circuit Arrangement for Testing Electrical Modules
Integratable, Controllable Delay Device, Use of a Delay Device, as Well as an Integratable Multiplexer for Use in a Delay Device
Method for Fabricating a Stacked Capacitor Array Having a Regular Arrangement of a Plurality of Stacked Capacitors
Field Effect Semiconductor Switch and Method for Fabricating It
Monitoring Device for Monitoring Internal Signals During Initialization of an Electronic Circuit
Computer-Supported, Automated Method for the Verification of Analog Circuits
Integrated Circuit
Input Circuit for an Electronic Circuit and a Method for Controlling the Reading-in of a Data Signal
Parallel-Serial Converter
Semiconductor Component with Internal Heating
Integrated Module Having a Plurality of Separate Substrates
Integrated Circuit for Determining a Voltage
Integrated Circuit
Write/Delete Process for Resistive Switching Memory Components
Reducing Current Consumption for Input Circuit of an Electronic Circuit
Method for Testing an Integrated Semiconductor Memory with a Shortened Reading Time
Method and Apparatus for Measuring a Surface Profile of a Sample
System for Determining a Reference Level and Evaluating a Signal on the Basis of the Reference Level
Fabrication Method for a Semiconductor Structure
Integrated Semiconductor Circuit and Method for Testing the Same
Electronic Memory Apparatus, and Method for Deactivating Redundant Bit Lines or Word Lines
Masks for Lithographic Imagings and Methods for Fabricating the Same
Integrated Circuit Including Memory Cell for Storing an Information Item and Method
Memory Circuit and Method for Providing an Item of Information for a Prescribed Period of Time
Method for the Formation of a Structure Size Measured Value
Stacked Capacitor Array and Fabrication Method for a Stacked Capacitor Array
Method for Testing a Memory Chip and Test Arrangement
Method and Circuit Arrangement for Controlling Write Access to a Semiconductor Memory
Method for Production of Trench Dram Cells and a Trench Dram Cell Array with Fin Field-Effect Transistors with a Curved Channel (Cfet - Curved Fets)
Method and Circuit Arrangement for Resetting an Integrated Circuit
Dram Memory Cell Arrangement
Method for Testing an Integrated Semiconductor Memory
Integrated Semiconductor Memory
Integrated Circuit for Stabilizing a Voltage
Method for Fabricating Dielectric Mixed Layers and Capacitive Element and Use Thereof
Fabrication Method for a Semiconductor Structure Having Integrated Capacitors
Backwards-Compatible Memory Module
Semiconductor Chip with Metallization Levels, and a Method for Formation of Interconnect Structures
Input Circuit for Receiving an Input Signal, and a Method for Adjusting an Operating Point of an Input Circuit
Method for Activating and Deactivating Electronic Circuit Units and Circuit Arrangement for Carrying Out the Method
Thin Film Field Effect Transistor with Gate Dielectric Made of Organic Material and Method for Fabricating the Same
Memory Circuit, and Method for Reading Out Data Contained in the Memory Circuit Using Shared Command Signals
Integrated Circuit
Read Latency Control Circuit
Electronic Circuit Apparatus and Method for Stacking Electronic Circuit Units
Integrated Circuit
Integrated Semiconductor Memory Comprising at Least One Word Line and Comprising a Multiplicity of Memory Cells
Integrated Semiconductor Memory
Memory Circuit Comprising Redundant Memory Areas
Test Apparatus and Method for Testing Circuit Units to Be Tested
Method for Forming Trench Memory Cell Structures for Drams
Method for Connecting an Integrated Circuit to a Substrate and Corresponding Circuit Arrangement
Method for Producing a Package for an Electronic Circuit and a Substrate for a Package
Memory Device with Multistage Sense Amplifier
Semiconductor Memory Device
Method for Determining a Matrix of Transmission Cross Coefficients in an Optical Proximity Correction of Mask Layouts
Device and a Process for the Calibration of a Semiconductor Component Test System
Method for Fabricating a Dram Memory Cell Arrangement Having Fin Field Effect Transistors and Dram Memory Cell
Method for Adapting Structure Dimensions During the Photolithographic Projection of a Pattern of Structure Elements Onto a Semiconductor Wafer
Digital Ram Memory Circuit with an Expanded Command Structure
Semiconductor Circuit Device and a System for Testing a Semiconductor Apparatus
Method for Correcting Structure-Size-Dependent Positioning Errors in Photolithography
Method for Production of a Standard Cell Arrangement, and Apparatus for Carrying Out the Method
Device for the regulated delay of a clock signal
Application:
11/194,510 →
Publication:
US 2006/0022737
Semiconductor and Method for Producing a Semiconductor
Clock Signal Synchronizing Device, and Clock Signal Synchronizing Method
Self Test for the Phase Angle of the Data Read Clock Signal Dqs
Clock Recovery Circuit and a Memory Device Employing the Same
Control System for a Dynamic Random Access Memory and Method of Operation Thereof
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.