Integrated memory circuit
View Patent ↗In a memory circuit integrated on a semiconductor chip, an interface system is formed between the connection pads and associated internal signal lines and contains a respective separate and complete interface circuit for each of at least two different modes of operation of the memory circuit. Each interface circuit is arranged distributed over a plurality of spaced sections of the chip surface such that sections of different interface circuits alternate with one another. Only the interface circuit which is associated with the mode of operation which is desired when the memory circuit is being used is operatively connected between the connection pads and the associated internal signal lines by metallizations in the topmost metallization plane.
1. A memory circuit integrated on a semiconductor chip, comprising:
at least one memory bank having a plurality of memory cells and a plurality of memory bank connections for accessing the memory cells for reading and writing data;
a plurality of connection pads connectable to external supply lines for transferring incoming and outgoing signals; and
an interface system for transferring signals between the plurality of connection pads and a plurality of internal signal lines connected to the plurality of memory bank connections, wherein the interface system comprises a plurality of interface circuits, each interface circuit corresponding to a different one of a plurality of modes of operation of the memory circuit, wherein each interface circuit is disposed in a plurality of separate sections, and wherein at least one of the plurality of interface circuits associated with a selected mode of operation of the plurality of modes of operation for the memory circuit is operatively connected between the plurality of internal signal lines and the plurality of connection pads by a metallization structure in a topmost metallization plane of the semiconductor chip.
2. The memory circuit of claim 1 , wherein the plurality of connection pads, the interface system and the plurality of internal signal lines are disposed in regions of the semiconductor chip which are situated outside of surface regions over the at least one memory bank.
3. The memory circuit of claim 1 , wherein, for each mode of operation of the memory circuit, a respective configuration of the interface system is implemented as a separate interface circuit containing all circuit elements for the respective configuration.
4. The memory circuit of claim 3 , wherein each interface circuit is distributed over a plurality of spaced sections of a chip surface so that sections of different interface circuits alternate with one another.
5. The memory circuit of claim 1 , wherein the plurality of connection pads comprises n≧2 data pads for incoming and outgoing data.
6. The memory circuit of claim 5 , wherein the interface system is configured to control data transfer between the data pads and the plurality of internal signal lines which are connected to the plurality of data connections of the at least one memory bank.
7. The memory circuit of claim 5 , wherein the n data pads are arranged in a row extending along an internal data bus.
8. The memory circuit of claim 7 , wherein n successive subregions of the interface system are integrated along the row of data pads, with each subregion respectively containing m sections corresponding to the plurality of interface circuits.
9. The memory circuit of claim 8 , wherein the plurality of memory banks comprise an even number of memory banks arranged in two rows on both sides of a chip surface region which extends in a first direction to form a primary channel containing the internal data bus and the row of data pads, wherein adjacent memory banks in each row of memory banks have a respective chip surface region between them as a subsidiary channel which extends at right angles to the primary channel and contains the signal lines routed to the data connections of the memory banks.
10. The memory circuit of claim 9 , wherein the total number q of subregions in the interface system is greater than n, and wherein at least some of the remaining q–n subregions of the interface system are integrated in the subsidiary channel.
11. The memory circuit of claim 1 , wherein plurality of modes of operation of the memory circuit is selectably configurable between a single data rate mode and a double data rate mode.
12. A method for configuring a memory circuit, comprising:
providing, in a configurable layer, a plurality of connection pads connectable to external lines for transferring incoming and outgoing signals;
providing an interface system for transferring signals between the plurality of connection pads and a plurality of internal signal lines connected to a plurality of memory banks, wherein the interface system comprises a plurality of interface circuits corresponding to a plurality of modes of operation of the memory circuit, wherein each interface circuit is disposed in a plurality of separate sections, wherein each section of each interface circuit includes one or more connections to one or more contact pairs in the configurable layer; and
selectively connecting the plurality of connection pads to a selected interface circuit of the plurality of interface circuits associated with a selected mode of operation of the plurality of modes of operation for the memory circuit by bridging one or more respective contact pairs connected to the selected interface circuit, and wherein the selected interface circuit associated with the selected mode of operation for the memory circuit is operatively connected between the plurality of internal signal lines and the plurality of connection pads by a metallization structure in a topmost metallization plane of the memory circuit.
13. The method of claim 12 , wherein the plurality of separate sections of the plurality of interface circuits are disposed in an interleaved arrangement.
14. The method of claim 12 , wherein the plurality of separate sections correspond in number to the plurality of connection pads.
15. The method of claim 12 , wherein the interface system is configured to control data transfer between the plurality of pads and the plurality of internal signal lines which are connected to a plurality of data connections of a plurality of memory banks.
16. An integrated circuit, comprising:
a first layer of the integrated circuit comprising a plurality of internal signal lines;
a second layer of the integrated circuit comprising a plurality of interface circuits; and
a third layer of the integrated circuit comprising a plurality of connection pads for connecting to external line, wherein the plurality of interface circuits are configured to control communication between the plurality of internal signal lines and the plurality of connection pads, wherein the plurality of interface circuits corresponds to a plurality of modes of operation of the integrated circuit, wherein each interface circuit is disposed in a plurality of separate sections, and wherein a selected interface circuit of the plurality of interface circuits associated with a selected mode of operation for the integrated circuit is operatively connected between the plurality of internal signal lines and the plurality of connection pads by a metallization structure in a topmost metallization plane of the integrated circuit.
17. The system of claim 16 , wherein the plurality of separate sections of the plurality of interface circuits are disposed in an interleaved arrangement.
18. The system of claim 16 , wherein the integrated circuit is a memory circuit selectably configurable between a single data rate mode and a double data rate mode.
19. The system of claim 16 , wherein the plurality of separate sections correspond in number to the plurality of connection pads.