Patent Assignment
Reel/Frame 036877/0513
Assignment of Assignor's Interest
Recorded: 2015-10-16
Pages: 13
Assignor
INFINEON TECHNOLOGIES AG
Executed: 2015-07-08
Assignee
POLARIS INNOVATIONS LIMITED
29 EARLSFORT TERRACE, DUBLIN 2, DUBLIN, IRELAND
Covered Properties
(201)
Semiconductor device and method of increasing channel length to eliminate short channel effects of corner devices
Patent:
6,365,947 →
Application:
09/559,776 →
Scanning Tip Orientation Adjustment Method for Atomic Force Microscopy
Apparatus for Patterning a Semiconductor Wafer
Continuous Test Flow Method and Apparatus
Method for Applying Rewiring to a Panel While Compensating for Position Errors of Semiconductor Chips in Component Positions of the Panel
Semiconductor Memory Device and Method for Operating a Semiconductor Memory Device
Clock Receiver Circuit Device, in Particular for Semi-Conductor Components
Semiconductor Device with Plastic Package Molding Compound, Semiconductor Chip and Leadframe and Method for Producing the Same
Voltage Regulation System
Method for Determining a Radiation Power and an Exposure Apparatus
Method of Forming Shallow Trench Isolation Using Deep Trench Isolation
Methods and Apparatus for Active Termination of High-Frequency Signals
Multi-Layer Barrier Allowing Recovery Anneal for Ferroelectric Capacitors
Formation of a Contact in a Device, and the Device Including the Contact
Fabrication of a Feram Capacitor Using a Noble Metal Hardmask
Off Chip Driver
Memory Cell Signal Window Testing Apparatus
Reduced Power Consumption in Integrated Circuits with Fuse Controlled Redundant Circuits
Reference Voltage Detector for Power-on Sequence in a Memory
Reliable Ferro Fuse Cell
Automated Layout Transformation System and Method
Random Access Memory Having Driver for Reduced Leakage Current
Memory Device Having Multiple Array Structure for Increased Bandwidth
Memory System with Reduced Refresh Current
Patent:
6,862,238 →
Application:
10/672,244 →
Temperature Sensor Scheme
Method for Producing a Ferroelectric Capacitor That Includes Etching with Hardmasks
Random Access Memory with Post-Amble Data Strobe Signal Noise Rejection
System and Method for Automatically-Detecting Soft Errors in Latches of an Integrated Circuit
Echo Clock on Memory System Having Wait Information
Device and a Method for Forming a Ferroelectric Capacitor Device
Device and a Method for Forming a Capacitor Device
Self-Aligned Vo-Contact for Cell Size Reduction
Method and Circuit Configuration for Digitizing a Signal in an Input Buffer of a Dram Device
Reference Current Distribution in Mram Devices
Mask and Method for Using the Mask in Lithographic Processing
Method and Circuit Configuration for Multiple Charge Recycling During Refresh Operations in a Dram Device
Patent:
6,847,566 →
Application:
10/692,119 →
Acoustic Detection of Mechanically Induced Circuit Damage
Method of Calculating a Pressure Compensation Recipe for a Semiconductor Wafer Implanter
Utilization of an Ion Gauge in the Process Chamber of a Semiconductor Ion Implanter
Device and Method for Inhibiting Oxidation of Contact Plugs in Ferroelectric Capacitor Devices
Ferroelectric Capacitor Devices and a Method for Compensating for Damage to a Capacitor Caused by Etching
Refresh for Dynamic Cells with Weak Retention
Latch Scheme with Invalid Command Detector
Patent:
6,839,288 →
Application:
10/706,146 →
Ferroelectric Capacitor Devices and Feram Devices
Method and Circuit Configuration for Refreshing Data in a Semiconductor Memory
Low Rise/Fall Skewed Input Buffer Compensating Process Variation
Internal Voltage Generator with Temperature Control
Back-Bias Voltage Generator with Temperature Control
Dual Power Sensing Scheme for a Memory Device
Methods and Apparatus for Active Termination of High-Frequency Signals
Random Access Memory with Optional Inaccessible Memory Cells
Imprint Suppression Circuit Scheme
Random Access Memory Using Precharge Timers in Test Mode
Method and Apparatus for Controlling Refresh Cycles of a Plural Cycle Refresh Scheme in a Dynamic Memory
Input Buffer Circuit Including Reference Voltage Monitoring Circuit
Oscillator with Temperature Control
Input Buffer with Differential Amplifier
Patent:
6,891,763 →
Application:
10/744,804 →
Temperature Compensated Delay Signals
Burst Mode Implementation in a Memory Device
Memory with Auto Refresh to Designated Banks
Patent:
6,859,407 →
Application:
10/757,275 →
Memory Device with Non-Variable Write Latency
Method for Formation of an Ultra-Thin Film and Semiconductor Device Containing Such a Film
Method of Determining the Overlay Accuracy of Multiple Patterns Formed on a Semiconductor Wafer
Method and Arrangement for Controlling Focus Parameters of an Exposure Tool
Memory Device with Common Row Interface
Method for Protecting the Redistribution Layer on Wafers/Chips
Voltage Level Converter Device
Method for Detecting and Compensating for Positional Displacements in Photolithographic Mask Units and Apparatus for Carrying Out the Method
Dram Memory Circuit with Sense Amplifiers
Arrangement for Reducing Stress in Substrate-Based Chip Packages
Method for Fabricating a Semiconductor Memory Having Charge Trapping Memory Cells and Semiconductor Substrate
Semiconductor Memory with Virtual Ground Architecture
Substrate-Based Chip Package
Method and Apparatus for Positioning a Test Head on a Printed Circuit Board
Method and Structure of an Auxiliary Transistor Arrangement Used for Fabricating a Semiconductor Memory Device
Substrate-Based Ic Package
Memory System and Method for Transferring Data Therein
Semi-Conductor Component Test Process and a System for Testing Semi-Conductor Components
System and Method for Determining the Temperature of a Semiconductor Wafer
Hub Chip for One or More Memory Modules
Noninvasive Method for Characterizing and Identifying Embedded Micropatterns
Integrated Circuit Having a Plurality of Output Drivers
Apparatus and Method for Calibrating a Semiconductor Test System
Method for Wireless Data Interchange Between Circuit Units Within a Package, and Circuit Arrangement for Performing the Method
Void Free, Silicon Filled Trenches in Semiconductors
Adapter Card for Connection to a Data Bus in a Data Processing Unit and Method for Operating a Ddr Memory Module
Semiconductor Memory Module
Semiconductor Memory Module
Output Driver for an Integrated Circuit and Method for Driving an Output Driver
Apparatus and Method for Reading Out Defect Information Items from an Integrated Chip
Method and Apparatus for Producing a Reference Voltage
Method for Fabricating a Trench Capacitor with an Insulation Collar Which Is Electrically Connected to a Substrate on One Side via a Buried Contact, in Particular for a Semiconductor Memory Cell
A Circuit and Method for Testing a Circuit Having Memory Array and Addressing and Control Unit
Semiconductor Memory Having Charge Trapping Memory Cells
Semiconductor Memory Module
Semi-Conductor Memory Component, and a Process for Operating a Semi-Conductor Memory Component
Charge Trapping Memory Cell
Method for Checking Periodic Structures on Lithography Masks
Method for Fabricating a Gate Structure of a Fet and Gate Structure of a Fet
Apparatus for Measuring an Exposure Intensity on a Wafer
Method of Making Contact with Circuit Units to Be Tested in a Tester and Contact-Making Apparatus for Implementing the Method
Method for Fabricating Trench Capacitor with Insulation Collar Electrically Connected to Substrate Through Buried Contact, in Particular, for a Semiconductor Memory Cell
Connector
Semiconductor Circuit and Method for Testing, Monitoring and Application-Near Setting of a Semiconductor Circuit
Memory Arrangement in a Computer System
Semiconductor Memory Module
Memory Cell with Nanocrystals or Nanodots
Apparatus and Method for Testing Circuit Units to Be Tested
Integrated Memory Having a Circuit for Testing the Operation of the Integrated Memory, and Method for Operating the Integrated Memory
Method for Projection of a Circuit Pattern, Which Is Arranged on a Mask, Onto a Semiconductor Wafer
Integrated Circuit for Testing Circuit Components of a Semiconductor Chip
Integrated Memory Having a Test Circuit for Functional Testing of the Memory
Address Decoding Circuit and Method for Addressing a Regular Memory Area and a Redundant Memory Area in a Memory Circuit
Test Arrangement for Testing Semiconductor Circuit Chips
Circuit for Distribution of an Input Signal to One or More Time Positions
Driver Device, in Particular for a Semiconductor Device, and Method for Operating a Driver Device
Semiconductor Memory Module
Sense Amplifier Connecting/Disconnecting Circuit Arrangement and Method for Operating Such a Circuit Arrangement
Fbga Arrangement
Memory Module and Method for Operating a Memory Module
Lithography Mask for Imaging of Convex Structures
Integrated Semiconductor Memory
Test Structure for a Single-Sided Buried Strap Dram Memory Cell Array
Method and Apparatus for Checking Output Signals of an Integrated Circuit
Process for Sealing Plasma-Damaged, Porous Low-K Materials
Differential Amplifier Circuit
Method for Forming a Trench in a Layer or a Layer Stack on a Semiconductor Wafer
Method for Fabricating an Integrated Circuit Device with Through-Plating Elements and Terminal Units
Arrangement for Producing an Electrical Connection Between a Bga Package and a Signal Source, and Method for Producing Such a Connection
Method of Fabricating an Interconnection for Chip Sandwich Arrangements
Interconnection Element for Bga Housings and Method for Producing the Same
Semiconductor Device with Test Circuit Disconnected from Power Supply Connection
Method for Testing Circuit Units to Be Tested and Test Apparatus
Circuit Arrangement for Setting a Voltage Supply for a Test Mode of an Integrated Memory
Circuit for Setting One of a Plurality of Organization Forms of an Integrated Circuit and Method for Operating It
Integrated Memory and Method for Functional Testing of the Integrated Memory
Method for Carrying Out a Double or Multiple Exposure
Signal Test Procedure for Testing Semi-Conductor Components and a Test Apparatus for Testing Semi-Conductor Components
Apparatus for Testing a Memory Module
Method for Determining the Relative Positional Accuracy of Two Structure Elements on a Wafer
Substrate for Producing a Soldering Connection
Nonvolatile Integrated Semiconductor Memory
Alignment Mark for Coarse Alignment and Fine Alignment of a Semiconductor Wafer in an Exposure Tool
Method for Detecting Positioning Errors of Circuit Patterns During the Transfer by Means of a Mask into Layers of a Substrate of a Semiconductor Wafer
Phase Shift Mask
Method for Fabricating Memory Cells and Memory Cell Array
Method for the Characterization of a Film
Method for Producing a Multichip Module and Multichip Module
Lithographic Mask, and Method for Covering a Mask Layer
Charge Trapping Memory Cell
Method for Fabricating Memory Components
Integrated Memory Circuit
Method for Operating a Memory Cell Array
Long Running Test Method for a Circuit Design Analysis
Method for Testing Circuit Units to Be Tested by Means of Majority Decisions and Test Device for Performing the Method
Method for Fabricating a Semiconductor Structure with an Encapsulation of a Filling Which Is Used for Filling Trenches
Wafer Level Packages for Chips with Sawn Edge Protection
Process for Generating a Hard Mask for the Patterning of a Layer
Level Converter
Clock Signal Synchronizing Device, and Clock Signal Synchronizing Method
Trench Capacitor Structure and Process for Applying a Covering Layer and a Mask for Trench Etching Processes in Semiconductor Substrates
Apparatus and Method for Proof of Outgassing Products
Transistor Structure, Memory Cell, Dram, and Method for Fabricating a Transistor Structure in a Semiconductor Substrate
Pseudodynamic Off-Chip Driver Calibration
Memory Cell and Method for Fabricating It
Method and Imaging Apparatus for Imaging a Structure Onto a Semiconductor Wafer by Means of Immersion Lithography
Input Switching Arrangement for a Semiconductor Circuit and Test Method for Unidirectional Input Drivers in Semiconductor Circuits
Method for Improving a Simulation Model of Photolithographic Projection
Electronic Component with Compliant Elevations Having Electrical Contact Areas and Method for Producing It
Method for Producing an Integrated Memory Module
Circuit
Charge Transfer Complexes Including an Electron Donor and an Electron Acceptor as Basis of Resistive Memories
Transistor Structure with a Curved Channel, Memory Cell and Memory Cell Array for Drams, and Methods for Fabricating a Dram
Memory Component with Improved Noise Insensitivity
Method for Fabricating Contact-Making Connections
Semiconductor Memory Device with Write Protected Memory Banks
Process for Producing Metallic Interconnects and Contact Surfaces on Electronic Components
Process for Producing Layer Structures for Signal Distribution
Method for Matching Two Measurement Methods for Measuring Structure Widths on a Substrate
Semiconductor Memory Having a First and Second Sense Amplifier for Sensing a Memory Cell Voltage During a Normal Mode and a Refresh Mode
Method for Smoothing Areas in Structures by Utilizing the Surface Tension
Method and Circuit Arrangement for Testing Electrical Modules
Device for Generating and/or Influencing Electromagnetic Radiation from a Plasma
Clock Recovery Circuit and a Memory Device Employing the Same
Compound Used to Form a Self-Assembled Monolayer, Layer Structure, Semiconductor Component Having a Layer Structure, and Method for Producing a Layer Structure
Control System for a Dynamic Random Access Memory and Method of Operation Thereof
Semiconductor Module for Making Electrical Contact with a Connection Device via a Rewiring Device
Device and Method for Testing an Electrical Circuit
Device and Method for Testing an Electric Circuit
Self-Aligned V0-Contact for Cell Size Reduction
Clock Signal Input/Output Device for Correcting Clock Signals
Integrated Circuit with Electrostatic Discharge Protection
Synchronous Ram Memory Circuit
Memory Arrangement Having a Plurality of Ram Chips
Magnetoresistive Memory Cell and Process for Producing the Same
Integrated Semiconductor Memory
Integrated Circuit, Test System and Method for Reading Out an Error Datum from the Integrated Circuit
Integrated Circuit Having a Resistive Memory
Method for Fabricating a Nanoelement Field Effect Transistor with Surrounded Gate Structure
Memory System and Method for Transferring Data Therein
Method for Fabricating a Nanoelement Field Effect Transistor with Surrounded Gate Structure
Related Assignments
(2)
Other recorded transfers of the patents in this record — the chain of ownership.