Input switching arrangement for a semiconductor circuit and test method for unidirectional input drivers in semiconductor circuits
View Patent ↗Transfer switching devices, which supplement unidirectional input switching arrangements or pad circuits are employed to route an internal test signal to the input of an input driver in the unidirectional input switching arrangement and to couple the internal test signal to an internal switching logic unit. The transfer switching devices are controlled via a multiplexer unit, which can be programmed directly using boundary scan registers. The present invention allows all unidirectional pad circuits or input drivers to be tested in the course of a reduced I/O test method for semiconductor circuits, in which testing internal circuits in the semiconductor circuit involves only a subset of the signal connections associated with the input drivers being coupled to a test apparatus.
1. A unidirectional input switching arrangement for a circuit, comprising:
a signal connection configured to couple with and receive an input signal from a test apparatus;
a unidirectional input driver connected to the signal connection via an input of the input driver, the unidirectional input driver being operable to condition the input signal applied to the signal connection into an internal input signal to be processed by internal circuits, wherein the internal circuits are coupled via a connection line to an output of the input driver; and
a transfer switching device, which is configured to be controlled by a test control signal and which, during a test mode of the circuit, is configured to couple the input of the input driver to a test signal line, wherein the test signal line is configured to route a test signal to the input of the input driver to facilitate testing of a parameter of the input driver.
2. The input switching arrangement as claimed in claim 1 , further comprising:
a bypass switching device configured to route the test signal transmitted on the test signal line to the transfer switching device or to the connection line that couples the output of the input driver to the internal circuits.
3. The input switching arrangement as claimed claim 1 , wherein a signal path between the signal connection and the transfer switching device is produced in isolation from a connecting line which couples the signal connection to the input driver.
4. A circuit, comprising:
internal circuits operable for processing and generating signals;
a plurality of input switching arrangements, each input switching arrangement including:
a signal connection configured to couple with and receive an input signal from a test apparatus;
a unidirectional input driver connected to the signal connection via an input of the input driver, the unidirectional input driver being operable to condition the input signal applied to the signal connection into an internal input signal to be processed by the internal circuits, wherein the internal circuits are coupled via a connection line to an output of the input driver; and
a transfer switching device, which is configured to be controlled by a test control signal and which, during a test mode of the circuit, is configured to couple the input of the input driver to a test signal line, wherein the test signal line is configured to route a test signal to the input of the input driver to facilitate testing of a parameter of the input driver.
5. The semiconductor circuit as claimed in claim 4 , further comprising:
a multiplexer unit which, during a test mode in the semiconductor circuit, controls the switching devices in the input switching arrangement, the multiplexer unit comprising:
first multiplexer switching devices configured to route the test control signals;
second multiplexer switching devices configured to route the test signal from a test signal source to an input driver to be tested;
third multiplexer switching devices configured to route an output signal from respective input drivers to be tested to an evaluation unit; and
register units configured to control the state of switching devices in the input switching arrangement and the first, second, and third multiplexer switching devices.
6. The semiconductor circuit as claimed in claim 5 , further comprising at least one of an internal evaluation unit and a test signal source configured to output the test signal.
7. The semiconductor circuit as claimed in claim 5 , further comprising:
a test port configured to control the multiplexer unit.
8. A method for testing a circuit comprising a plurality of unidirectional input switching arrangements each including a signal connection, and internal circuits connected to the input switching arrangements, the method comprising:
coupling a respective first subset of the signal connections to a test apparatus;
testing the internal circuits in a test mode using the first subset of the signal connections;
coupling at least one second subset of signal connections which is not contained in the first subset to internal test signal lines on the basis of test control signals generated in the test mode;
generating a test signal transmitted on the test signal line; and
using the internal test signal lines to test the input switching arrangements associated with the second subset of signal connections.
9. The method as claimed in claim 8 , further comprising:
coupling the input of the input switching arrangement to a test signal source via the test signal line, and coupling the output of the input switching arrangement to an evaluation unit;
recording a driver propagation time for a test signal transmitted from the test signal source to the evaluation unit;
using a bypass switching device to bypass the switching device and an input driver in the input switching arrangement, and recording a bypass propagation time for a second test signal transmitted from the test signal source to the evaluation unit; and
using the difference between the driver propagation time and the bypass propagation time to ascertain the propagation time delay for the input driver.