Method for fabricating a semiconductor memory having charge trapping memory cells and semiconductor substrate

1. A method for fabricating a semiconductor memory having charge trapping memory cells, the method comprising:

forming isolation regions in a semiconductor body;

forming channel regions of memory transistors in the semiconductor body;

forming a dielectric storage layer sequence over the channel regions, the dielectric storage layer sequence comprising a first boundary layer, a storage layer and a second boundary layer;

applying a first electrically conductive material over the semiconductor body;

patterning the first electrically conductive material to form word lines that run parallel at a distance from one another;

forming source/drain regions by introducing dopant in the semiconductor body adjacent the word lines;

introducing a second electrically conductive material between ones of the word lines; and

partially removing the second electrically conductive material using a mask in such a way that residual portions of the second electrically conductive material fills a section of a the space between two word lines and produces an electrical contact with at least one of the source/drain regions.

2. The method as claimed in claim 1 and further comprising introducing dielectric material into interspaces between the word lines and the residual portions of the second electrically conductive material.

3. The method as claimed in claim 2 wherein, the residual portions of the second electrically conducive material are arranged in such a way that, in accordance with a consecutive numbering of the source/drain regions along a respective word line, in the case of which source/drain regions, which are not arranged on different sides of an STI isolation, each acquire the same number, wherein:

on one side of the word line in each case an even-numbered source/drain region is electrically conductively connected to the subsequent odd-numbered source/drain region in said numbering, and

on the opposite side of this word line, in each case an odd-numbered source/drain region is electrically conductively connected to the subsequent even-numbered source/drain region in said numbering.

4. The method as claimed in claim 3 , and further comprising applying third electrically conductive material in strip form for the purpose of forming bit lines that are arranged parallel at a distance from one another and transversely with respect to the word lines and is contact-connected with the second electrically conductive material in such a way that a respective bit line is electrically conductively connected to the portions of said electrically conductive material which are present successively along the bit line in each case in next but one interspaces between the word lines.

5. The method as claimed in claim 1 wherein the first boundary layer comprises an oxide layer, the storage layer comprises a nitride layer, and the second boundary layer comprises an oxide layer.

6. The method as claimed in claim 1 wherein the first electrically conductive material is additionally patterned to form portions of an alignment mark, and the second electrically conductive material is also patterned to form further portions of the alignment mark.

7. The method as claimed in claim 6 wherein first electrically conductive material is patterned to form a mark border and wherein the second electrically conductive material is introduced as filling into a volume surrounded by the mark border.

8. The method as claimed in claim 1 the second electrically conductive material comprises tungsten.

9. A method for fabricating a semiconductor memory having charge trapping memory cells, in which:

in a first step, at a top side of a semiconductor body or substrate, in an arbitrary order, a concentration of dopant that suffices for forming channel regions of memory transistors is provided and strip-type STI isolations arranged parallel at a distance from one another are fabricated;

in a second step, a dielectric storage layer sequence comprising a first boundary layer, a storage layer and a second boundary layer is applied over the semiconductor body or substrate;

in a third step, electrically conductive material is applied and patterned together with a top-side insulation layer to form word lines, which run parallel at a distance from one another transversely with respect to the STI isolations;

in a fourth step, the word lines are electrically insulated laterally and source/drain regions are fabricated by introducing dopant between the STI isolations and the word lines; and

in a fifth step, electrically conductive material is introduced into interspaces between the word lines and is partially removed using a mask in such a way that residual portions of the electrically conductive material in each case fill a section of the relevant interspace and produce an electrical contact with in each case at least one of the source/drain regions.

10. The method as claimed in claim 9 , in which, in a sixth step, dielectric material is in each case introduced into interspaces between the word lines and the residual portions of the electrically conductive material.

11. The method as claimed in claim 10 , in which,

in the fifth step, the residual portions of the electrically conducive material are arranged in such a way that, in accordance with a consecutive numbering of the source/drain regions along a respective word line, in the case of which the source/drain regions which are not arranged on different sides of an STI isolation each acquire the same number,

a) on one side of the word line in each case an even-numbered source/drain region is electrically conductively connected to the subsequent odd-numbered source/drain region in said numbering, and

b) on the opposite side of this word line, in each case an odd-numbered source/drain region is electrically conductively connected to the subsequent even-numbered source/drain region in said numbering.

12. The method as claimed in claim 11 , in which, in a seventh step, electrically conductive material is applied in strip form for the purpose of forming bit lines which are arranged parallel at a distance from one another and transversely with respect to the word lines and is contact-connected with the electrically conductive material introduced in the fifth step in such a way that a respective bit line is electrically conductively connected to the portions of said electrically conductive material which are present successively along the bit line in each case in next but one interspaces between the word lines.

13. The method as claimed in claim 9 , in which, in the second step, an oxide layer is fabricated as the first boundary layer, a nitride layer is fabricated as the storage layer, and an oxide layer is fabricated as the second boundary layer.

14. The method as claimed in claim 9 , in which,

in the third step, the electrically conductive material and the insulation layer are additionally patterned to form portions of an alignment mark, and

in the fifth step, the electrically conductive material is also patterned to form further portions of the alignment mark.

15. The method as claimed in claim 14 , in which,

in the third step, the portions of the alignment part are patterned as mark border, and

in the fifth step, the electrically conductive material is introduced as filling into a volume surrounded by the mark border.

16. The method as claimed in claim 9 , in which, in the fifth step, tungsten is introduced as electrically conductive material.