Integrated memory and method for functional testing of the integrated memory
View Patent ↗An integrated memory includes memory cells arranged in a memory cell array along word lines and bit lines. One of the bit lines can be connected to a data line by a respective one of a plurality of switches. The memory contains column select lines. One of the column select lines in each case connected to a plurality of the switches for driving, in an activated state, in order to connect a number of bit lines to a same number of data lines. An access controller is connected to the column select lines and can be operated in a test operating mode such that a plurality of the column select lines are activated in the event of a memory cell access. The writing of test data to the memory cell array in a test operating mode can thus be optimized in accordance with the invention.
1. An integrated memory, comprising:
a plurality of memory cells arranged in a memory cell array along word lines for selection of the memory cells and bit lines for reading out or writing data signals of the memory cells;
a plurality of switches, one of the bit lines being connected to a data line by a respective one of the switches;
a plurality of colunm select lines, one of the column select lines being connected to a plurality of the switches for driving the switches in an activated state in order to connect a number of bit lines to a same number of data lines;
an access controller being connected to the column select lines and operable in a test operating mode such that a plurality of the column select lines can be activated in the event of a memory cell access;
a plurality of sense amplifiers for evaluating and amplifying the data signals of the memory cells, the sense amplifiers each being connected to a respective bit line and arranged in a sense amplifier strip that subdivides the bit lines into two partial regions; and
a plurality of isolation switches for respectively coupling the partial regions of one of the bit lines to the sense amplifiers of the sense amplifier strip, the isolation switches being driven by the access controller such that the partial regions of one of the bit lines can be connected to a respective sense amplifier of the sense amplifier strip.
2. The integrated memory as claimed in claim 1 ,
wherein the data lines are assigned to one of the sense amplifier strips, and the access controller is operable such that the data lines assigned to a sense amplifier strip are connected to corresponding bit lines by one of the column select lines.
3. The integrated memory as claimed in claim 1 , wherein the memory cell array includes a plurality of regions of the same type, the integrated memory further comprising:
a crossing location at which the bit lines of one of the regions of the memory cell array cross with the bit lines of another of the regions.
4. The integrated memory as claimed in claim 1 , wherein the memory cell array includes a plurality of regions of the same type,
the column select lines are provided in each of the regions of the memory cell array, and
the access controller activates a plurality of the column select lines in one of the regions.
5. The integrated memory as claimed in claim 1 , wherein the bit lines are organized in bit line pairs, two bit lines of a bit line pair being connected to a shared sense amplifier.
6. The integrated memory as claimed in claim 1 , wherein the word lines are activated for a memory cell access by the access controller.
7. The integrated memory as claimed in claim 6 , wherein the word lines are activated simultaneously.
8. The integrated memory as claimed in claim 1 , wherein the partial regions of one of the bit lines are simultaneously connected to the respective sense amplifier.
9. A method for functional testing of an integrated memory including: a plurality of memory cells arranged in a memory cell array along word lines for selection of the memory cells and bit lines for reading out or writing data signals of the memory cells; a plurality of column select lines for driving a plurality of switches to respectively connect bits lines to data lines; an access controller operable in a test operating mode to activate the colunin select lines; a plurality of sense amplifiers respectively connected to bit lines and arranged in a sense amplifier strip that subdivides the bit lines into two partial regions; and a plurality of isolation switches for respectively coupling the partial regions of one of the bit lines to the sense amplifiers of the sense amplifier strip, the method comprising:
simultaneously activating the plurality of the column select lines by the access controller in the event of a memory cell aceess; and
driving the isolation switches by the access controller such that the partial regions of one of the bit lines are connected to a respective sense amplifier of the sense amplifier strip.
10. The method as claimed in claim 9 , further comprising:
simultaneously activating the word lines for a memory cell access by the access controller.
11. The method as claimed in claim 10 , further comprising:
simultaneously activating a group of the word lines by the access controller, the group including at least two of the word lines and at most a portion of the word lines; and
simultaneously activating a plurality of groups of word lines individually one after the other across the memory cell array.