Nonvolatile integrated semiconductor memory
View Patent ↗A nonvolatile integrated semiconductor memory has an arrangement of layers with a tunnel barrier layer and a charge-storing level. The charge-storing level has a dielectric material which stores scattered in charge carriers in a spatially fixed position. The tunnel barrier layer has a material through which high-energy charge carriers can tunnel. At least one interface surface of the charge-storing level has a greater microscopic roughness than the interface surface of the tunnel barrier layer, which is remote from the charge-storing level. The charge-storing level has a greater layer thickness in first regions than in second regions. This produces a relatively identical distribution and localization of positive and negative charge carriers in the lateral direction. The charge carriers which are scattered into the charge-storing level, therefore, recombine completely, so that the risk of unforeseen data loss during long-term operation of nonvolatile memories is reduced.
1. A nonvolatile integrated semiconductor memory, comprising:
a semiconductor substrate; and
an arrangement of layers including a tunnel barrier layer and a charge-storing level, the charge-storing level comprising a dielectric material that stores scattered-in charge carriers in a spatially fixed position, and the tunnel barrier layer having a common interface surface with the charge-storing level and a further interface surface that is remote from the charge-storing level, the tunnel barrier layer comprising a dielectric through which high-energy charge carriers can tunnel,
wherein at least one interface surface of the charge-storing level has a greater microscopic roughness than the further interface surface of the tunnel barrier layer that is remote from the charge-storing level, the charge-storing level having a greater layer thickness in first regions than in second regions.
2. The semiconductor memory as claimed in claim 1 , wherein the further interface surface of the tunnel barrier layer has a relatively low roughness such that the tunnel barrier layer levels out microscopic layer thickness fluctuations of the charge-storing level.
3. The semiconductor memory as claimed in claim 1 , wherein the tunnel barrier layer has a mean layer thickness of between 1 and 20 nm, and wherein roughness-induced local layer thickness fluctuations amount to at most 85% of the mean layer thickness of the tunnel barrier layer.
4. The semiconductor memory as claimed in claim 1 , wherein the tunnel barrier layer has a layer thickness that is constant in lateral directions.
5. The semiconductor memory as claimed in claim 1 , wherein the charge-storing level has a mean layer thickness of between 1 and 20 nm, and wherein roughness-induced local layer thickness fluctuations amount to at least 10% and at most 200% of the mean layer thickness of the charge-storing level.
6. The semiconductor memory as claimed in claim 1 , wherein the charge-storing level is formed from a plurality of laterally isolated island regions of the dielectric material.
7. The semiconductor memory as claimed in claim 1 , wherein the tunnel barrier layer is arranged directly on the surface of the semiconductor substrate and extends over a channel region of the semiconductor substrate between a first doped region and a second doped region.
8. The semiconductor memory as claimed in claim 1 , wherein the arrangement of layers includes two tunnel barrier layers and the charge-storing level is arranged between the two tunnel barrier layers.
9. The semiconductor memory as claimed in claim 7 , wherein the arrangement of layers is covered with a gate electrode that extends from a region above the first doped region to a region above the second doped region.
10. The semiconductor memory as claimed in claim 7 , wherein the charge-storing level above edge regions of the first doped region or the second doped region is locally electrically chargeable by high-energy charge carriers from the channel region.
11. The semiconductor memory as claimed in claim 7 , wherein the doped regions are source/drain regions of a memory structure of a storage transistor.
12. The semiconductor memory as claimed in claim 1 , wherein the dielectric material of the charge-storing level has a higher dielectric constant than the dielectric of the tunnel barrier layer.
13. The semiconductor memory as claimed in claim 1 , wherein the charge-storing level comprises at least one of an oxide, a nitride, and an oxynitride.
14. The semiconductor memory as claimed in claim 1 , wherein the tunnel barrier layer comprises an oxide.
15. The semiconductor memory as claimed in claim 14 , wherein the oxide is a silicon oxide.