IP Library Granted Patent US 7,035,160
Granted Patent B2
US 7,035,160 · App. 11/009,967 · Granted Apr 25, 2006

Circuit

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,035,160
App. No.
11/009,967
Granted
Apr 25, 2006
Kind
B2
Abstract

A circuit comprises a first supply line and a second supply line. A capacitor is arranged between the first supply line and the second supply line. The first supply line and the second supply line are inductively coupled, such that a switching current on the second supply line induces a compensating current into the first supply line. The compensating current compensates the switching current by flowing from the second supply line over the capacitor into the first supply line.

Claims (15)

1. A circuit comprising:

a first supply line for supplying a first voltage;

a second supply line for supplying a second voltage;

a switch for switching a signal voltage on a signal line between the first voltage and the second voltage; and

a capacitor arranged between the first supply line and the second supply line;

wherein the first supply line and the second supply line are inductively coupled, such that a switching current on the second supply line induces a compensating current into the first supply line; and

wherein the compensating current compensates the switching current by flowing from the second supply line over the capacitor into the first supply line.

2. The circuit according to claim 1 , wherein the switch for switching is an output stage of a circuit chip.

3. The circuit according to claim 1 , wherein the switch for switching comprises a first transistor and a second transistor, wherein the first transistor connects the first supply line and the signal line, and wherein the second transistor connects the signal line and the second supply line.

4. The circuit according to claim 2 , wherein the capacitor is an in-chip power supply decoupling circuitry of the circuit chip.

5. The circuit according to claim 1 , wherein the signal line is connected to the first supply line via a resistor.

6. The circuit according to claim 1 , wherein the first supply line and the second supply line are connected to a provider for providing the first voltage and the second voltage to the first supply line and the second supply line.

7. The circuit according to claim 1 , further comprising a coupling region in which the first supply line and the second supply line are routed in parallel such that the switching current on the second supply line induces the compensating current into the first supply line.

8. The circuit according to claim 1 wherein the first supply line and the second supply line are printed circuit board traces or wires of a TSSOP like package.

9. The circuit according to claim 2 , wherein the circuit chip is a mommy chip which is arranged on a circuit package board and wherein the first supply line and the second supply line connect the memory chip to terminals of the circuit package board.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036877/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 16, 2005
From: KUZMENKA, MAKSIM
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015905/0646 →