Method and circuit configuration for refreshing data in a semiconductor memory
View Patent ↗Methods and circuit configurations for refreshing data in a semiconductor memory device in which refresh operations are performed for a limited number of rows. The limited number of rows may include only those rows that contain valid data, for example, as determined by monitored write operations.
1. A method for selectively refreshing rows of memory cells in one or more semiconductor memory devices, comprising:
monitoring, by a memory controller coupled with the semiconductor memory devices, write operations to the memory cells;
maintaining a plurality of bits indicative of rows containing memory cells involved in the monitored write operations on the memory controller;
transferring a first plurality of the bits to a first memory device;
placing the first memory device in a self-refresh mode, in which refresh operations are performed for only those rows containing memory cells involved in the monitored write operations, as indicated by the first plurality of bits;
transferring a second plurality of the bits to a second memory device; and
placing the second memory device in a self-refresh mode, in which refresh operations are performed for only those rows containing memory cells involved in the monitored write operations, as indicated by the second plurality of bits.
2. The method of claim 1 , further comprising:
issuing a self-refresh command from the memory controller to the memory device.
3. A semiconductor memory device, comprising:
a plurality of rows of memory cells;
refresh circuitry configured to issue refresh requests for the rows of memory cells when the memory device is placed in a self-refresh mode;
row state circuitry configured to maintain a plurality of bits indicative of rows that are to be refreshed;
pins configured to receive the plurality of bits from a memory controller and to transfer the plurality of bits to the row state circuitry; and
refresh enable circuitry configured to limit the number of rows for which refresh requests are issued based on the bits of the row state circuitry, wherein the refresh enable circuitry is configured to limit the number of rows for which refresh requests are issued by generating a signal used to inhibit refresh requests.
4. The semiconductor memory device of claim 3 , wherein the signal is generated by accessing a bit corresponding to a row address generated by a refresh address counter.
5. The semiconductor memory device of claim 4 , wherein each bit corresponds to a single row of memory cells.
6. The memory device of claim 3 , wherein the memory controller is configured to issue a self-refresh command to the memory device.
7. A system, comprising:
a first memory device having a plurality of rows of memory cells, wherein the first memory device is configured to limit the number of rows that are refreshed, during a self-refresh mode, based on row data indicative of rows that are to be refreshed;
a second memory device having a plurality of rows of memory cells, wherein the second memory device is configured to limit the number of rows that are refreshed, during a self-refresh mode, based on row data indicative of rows that are to be refreshed; and
a memory controller configured to:
monitor write operations to the first memory device, generate the row data of the first memory device based on the monitored write operations, and transfer the row data of the first memory device to the first memory device prior to placing the memory device in the self-refresh mode, and;
monitor write operations to the second memory device, generate the row data of the second memory device based on the monitored write operations, and transfer the row data of the second memory device to the second memory device prior to placing the memory device in the self-refresh mode.
8. The system of claim 7 , wherein:
the row data is stored in the memory device in an array of memory cells; and
the memory controller is further configured to reset the array of memory cells prior to transferring the row data to the memory device.
9. The system of claim 8 , wherein the memory controller is configured to reset the array of memory cells by writing to a mode register of the memory device.
10. The system of claim 7 , wherein the memory controller is configured to set a bit in the row data to indicate one or more cells in a corresponding row have been written.
11. The memory device of claim 3 , wherein the plurality of bits is indicative of rows that have been written to and are to be refreshed.
12. The system of claim 7 , wherein the memory controller is configured to issue a self-refresh command to the memory device.