Clock signal input/output device for correcting clock signals
View Patent ↗The invention relates to a clock signal correction method, and to a clock signal input/output device into which a clock signal or a signal obtained therefrom is input and transmitted to a frequency divider, wherein a signal output by the frequency divider is transmitted to a signal integrator, and wherein a signal output by the signal integrator is transmitted to a first signal comparison circuit, wherein the signal output by the frequency divider is additionally transmitted to a second signal comparison circuit, and wherein the clock signal input/output device additionally comprises a signal input circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and of a signal output by the second signal comparison circuit.
1. A clock signal input/output device, comprising:
a frequency divider into which a clock signal or a signal obtained therefrom is input;
a signal integrator to receive a signal output by the frequency divider or a signal obtained therefrom;
a first signal comparison circuit to receive a signal output by the signal integrator or a signal obtained therefrom;
a second signal comparison circuit to be sent or receive the signal output by the frequency divider or the signal obtained therefrom;
a signal output circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and of a signal output by the second signal comparison circuit.
2. The clock signal input/output device according to claim 1 , wherein the clock output signal output by the signal output circuit further depends on another signal output by the first signal comparison circuit, and on a signal output by the second signal comparison circuit.
3. The clock signal input/output device according to claim 1 , wherein the clock output signal output by the signal output device further depends on a signal output by a third signal comparison circuit, and on a signal output by a fourth signal comparison circuit.
4. The clock signal input/output device according to claim 1 , wherein one or a plurality of the signal comparison circuits are receiver circuits.
5. The clock signal input/output device according to claim 4 , wherein the one or the plurality of receiver circuits comprise cross-coupled transistors.
6. The clock signal input/output device according to claim 1 , wherein the clock output signal output by the signal output circuit changes its state, at a positive edge of the signal output by the second signal comparison device, from logical low to logical high, or from logical high to logical low, and at a subsequent positive edge of the signal output by the first signal comparison circuit, back to logical low or logical high.
7. The clock signal input/output device according to claim 5 , wherein the clock output signal output by the signal output circuit changes its state, at a negative edge of the signal output by the second signal comparison circuit, from logical low to logical high, or from logical high to logical low, and at a subsequent negative edge of the signal output by the first signal comparison circuit back to logical low or logical high.
8. A clock signal correction method, comprising:
dividing the frequency of a clock signal so that a signal with a lower frequency vis-à-vis the frequency of the clock signal is obtained;
integrating the signal with the lower frequency so that an integration signal is obtained;
comparing the signal with the lower frequency with a signal that is inverse thereto; and
comparing the integration signal with a signal that is inverse thereto.
9. A clock signal input/output device, comprising:
a frequency divider to receive a clock signal;
a signal integrator to receive a signal output by the frequency divider or a signal obtained therefrom;
a first signal comparison circuit to receive a signal output by the signal integrator or a signal obtained therefrom;
a second signal comparison circuit to receive the signal output by the frequency divider or the signal obtained therefrom; and
a signal output circuit for outputting a clock output signal as a function of a signal output by the first signal comparison circuit, and a signal output by the second signal comparison circuit, wherein a signal edge of the clock output signal extending in a first direction is triggered by a signal edge of the signal output by the second signal comparison circuit, and a second signal edge of the clock output signal extending in a second direction opposite to the first direction is triggered by a signal edge of the signal output by the first signal comparison circuit.
10. A clock signal correction method, comprising:
dividing the frequency of a clock signal so that a signal with a lower frequency vis-à-vis the frequency of the clock signal is obtained;
integrating the signal with the lower frequency, so that an integration signal is obtained;
comparing the signal with the lower frequency with a signal that is inverse thereto, so that a first comparison signal is obtained;
comparing the integration signal with a signal that is inverse thereto, so that a second comparison signal is obtained; and
outputting a clock output signal, wherein a signal edge of the clock output signal extending in a first direction is triggered by a signal edge of the first comparison signal, and a signal edge of the clock output signal extending in a second direction opposite to the first direction is triggered by a signal edge of the second comparison signal.