IP Library Granted Patent US 7,001,781
Granted Patent B2
US 7,001,781 · App. 10/672,306 · Granted Feb 21, 2006

Method for producing a ferroelectric capacitor that includes etching with hardmasks

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Quick Facts
Patent No.
US 7,001,781
App. No.
10/672,306
Granted
Feb 21, 2006
Kind
B2
Abstract

A method for fabricating a device and a device, such as a ferroelectric capacitor, having a substrate, a contact plug through the substrate, a first barrier layer on the substrate, a first electrode on the first barrier layer, a dielectric layer on the first electrode, and a second electrode on the dielectric layer, comprises etching the second electrode and the dielectric layer of the device using a first hardmask, to shape the second electrode and the dielectric layer. The first hardmask is then removed and one or more encapsulating layers are applied to the second electrode and the dielectric layer. A further hardmask is applied to the one or more encapsulating layers. The first electrode is then etched according to the second hardmask down to the first barrier layer and the second hardmask is then removed from the one or more encapsulating layers.

Claims (15)

1. A method for fabricating a device having a substrate, a contact plug through the substrate, a first barrier layer on said substrate, a first electrode on said first barrier layer, a dielectric layer on said first electrode, and a second electrode on said dielectric layer, the method comprising the steps of:

forming a first hardmask over the second electrode;

etching said second electrode and said dielectric layer of said device, using said first hardmask to shape said second electrode and said dielectric layer;

removing said first hardmask;

applying one or more encapsulating layers to said second electrode and said dielectric layer;

applying a second hardmask to said one or more encapsulating layers;

etching said first electrode according to said second hardmask down to said first barrier layer; and

removing said second hardmask from said one or more encapsulating layers.

2. The method of claim 1 , further comprising etching said first barrier layer through to said substrate after the step of removing said second hardmask from one or more encapsulating layers.

3. The method of claim 2 , further comprising applying one or more cover layers to said devices after the step of etching said first barrier layer.

4. The method of claim 1 , further comprising annealing said device after the step of removing said first hardmask.

5. The method of claim 1 , wherein the step of removing said first hardmask comprises applying a dry etching process.

6. The method of claim 1 , wherein the step of removing said first hardmask comprises applying a dry etching process having a high etching selectivity of said dielectric layer relative to said first and/or said second electrode.

7. The method of claim 1 , wherein the step of forming a dielectric layer on said first electrode comprises forming a ferroelectric layer on said first electrode.

8. The method of claim 1 , wherein the step of etching said second electrode and said dielectric layer comprises etching said second electrode and said dielectric layer to divide the device into a number of devices having a common first electrode.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036877/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 8, 2004
From: LIAN, JINGYU; EGGER, ULRICH; ZHUANG, HAOREN
To: INFINEON TECHNOLOGIES AG
Reel/Frame 014860/0340 →