IP Library Granted Patent US 7,787,279
Granted Patent B2
US 7,787,279 · App. 11/441,805 · Granted Aug 31, 2010

Integrated circuit having a resistive memory

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,787,279
App. No.
11/441,805
Granted
Aug 31, 2010
Kind
B2
Abstract

An integrated semiconductor memory includes a storage medium ( 6 ) arranged between two electrodes ( 10, 20 ), which storage medium may be a phase change medium, for example. The storage medium ( 6 ) can be put into a first state or a second state by means of an electric current, as a result of which an item of information can be stored. According to embodiments of the invention, a layer plane (L) is provided in which impurity particles made from a material ( 4 ) are embedded, as a result of which the current density in the storage medium is locally increased and the programming current required for reprogramming is reduced. As a result, the current consumption of memory elements containing a phase change medium is reduced, so that for the first time they can be embodied with minimal feature size, together with other components such as transistors, and integrated into a single semiconductor circuit and no longer have to be arranged in separate subcircuits.

Claims (16)

1. An integrated circuit having a resistive memory comprising:

a first electrode;

a second electrode; and

a storage portion between the first electrode and the second electrode, the storage portion comprising a storage medium and regions made of a material different than the storage medium, the regions having dimensions smaller than a feature size that can be dimensioned with lithography used to pattern the storage medium, and the regions made from the different material comprising patterned regions of a patterned electrically insulating layer.

2. The integrated circuit as claimed in claim 1 , wherein the material is surrounded by the storage medium.

3. The integrated circuit as claimed in claim 1 , wherein the material is arranged directly on an interface with a carrier layer.

4. The integrated circuit as claimed in claim 3 , wherein the carrier layer comprises an electrode layer.

5. The integrated circuit as claimed in claim 4 , wherein an area proportion of the interface with the carrier layer of between 0.01% and 90% is covered by the storage medium.

6. The integrated circuit as claimed in claim 5 , wherein an area proportion of the interface with the carrier layer of between 0.01% and 5% is covered by the storage medium.

7. The integrated circuit as claimed in claim 5 , wherein an electric current flowing through the storage medium can be fed with the aid of the first and second electrodes.

8. The integrated circuit as claimed in claim 1 , wherein the storage medium is electrically conductively connected to the first electrode and to the second electrode.

9. The integrated circuit as claimed in claim 1 , wherein the regions made from the material comprise isolated islands having an average diameter of between 0.5 nm and 100 nm.

10. The integrated circuit as claimed in claim 1 , wherein the material comprises nanocrystalline particles or an amorphous insulator.

11. The integrated circuit as claimed in claim 1 , wherein the storage medium has a lower degree of crystallization in a first state and a higher degree of crystallization in a second state.

12. The integrated circuit as claimed in claim 1 , wherein the storage medium contains a chalcogenide or a pnicogenide.

13. The integrated circuit as claimed in claim 1 , wherein the resistive memory comprises a nonvolatile phase change memory.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036877/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 12, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023768/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 5, 2006
From: HAPP, THOMAS D.; PINNOW, CAY-UWE; SYMANCZYK, RALF; UFERT, KLAUS-DIETER
To: INFINEON TECHNOLOGIES AG
Reel/Frame 018201/0846 →