Memory cell and method for fabricating it

1. Method for fabricating a memory cell, having the following steps of:

a) providing a substrate,

b) patterning the substrate by etching a trench-type depression into the substrate,

c) producing a barrier layer in the trench-type depression of the substrate in such a way that the barrier layer covers an inner area of the trench-type depression only in a collar region forming an upper region of the trench-type depression;

d) growing grain elements on the inner areas of the trench-type depression, the surfaces of the grain elements together with the inner areas of the trench-type depression forming areas of a first electrode of the memory cell and grain elements being etched back in the collar region;

e) depositing a dielectric layer on the surfaces of the grain elements and the inner areas of the trench-type depression; and

f) depositing a conduction layer on the dielectric layer, the conduction layer forming a second electrode of the memory cell; wherein step d) of growing the grain elements on the inner areas of the trench-type depression comprises the following two substeps of:

d1) depositing an amorphous silicon layer on the barrier layer on the inner areas of the trench-type depression in such a way that the amorphous silicon layer is closed in the collar region, while the amorphous silicon layer does not form a closed structure in an electrode region forming a lower region of the trench-type depression; and

d2) selectively growing the grain elements on the inner areas of the trench-type depression in the electrode region, the amorphous silicon layer continuing to grow in the collar region of the trench-type depression.

2. Method according to claim 1 , wherein, in step b), a trench-type depression is etched into the substrate.

3. Method according to claim 1 , wherein, after step c) of producing the barrier layer in the electrode region of the trench-type depression, a sidewall etching is carried out for the purpose of widening the electrode region of the trench-type depression.

4. Method according to claim 1 wherein, after step d) of growing grain elements on the inner areas of the trench-type depression, a gas phase doping is carried out at the inner areas of the electrode region of the trench-type depression for the purpose of forming a doped first electrode of the memory cell.

5. Method according to claim 4 , wherein the gas phase doping at the inner areas of the electrode region of the trench-type depression provides a doping of the first electrode in the range of 10 −19 to 10 −20 cm −3 .

6. Method according to claim 5 , wherein the gas phase doping at the inner areas of the electrode region of the trench-type depression is carried out by means of arsine.

7. Method according to claim 1 , wherein a silicon nitride material and/or an aluminum oxide material is provided in the collar region of the trench-type depression.

8. Method according to claim 1 , wherein the grain elements grown on the inner areas of the trench-type depression are grown with a grain size in a range of 10 nm to 80 nm.

9. Method according to claim 1 , wherein a layer made of silicon dioxide is produced in the electrode region of the trench-type depression prior to growth of the grain elements.

10. Method according to claim 1 , wherein the grain elements grown on the inner areas of the trench-type depression are formed as hemispherical silicon grains.

11. Method according to claim 1 , wherein the conduction layer, which is deposited on the dielectric layer and which forms the second electrode of the memory cell, completely fills the trench-type depression.

12. Memory cell for storing electrical charge, having:

a) a substrate having a trench-type depression with a collar region forming an upper region of the trench-type depression and an electrode region forming a lower region of the trench-type depression;

b) grain elements on the inner areas of the trench-type depression, the surfaces of the grain elements together with the inner areas of the trench-type depression providing areas of a first electrode of the memory cell;

c) a dielectric layer deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, said dielectric layer providing a dielectric of the memory device; and

d) a conduction layer deposited on the dielectric layer, said conduction layer providing a second electrode of the memory cell; characterized in that an amorphous silicon layer is provided on the barrier layer on the inner areas of the trench-type depression in such a way that the amorphous silicon layer is closed in the collar region, while the amorphous silicon layer does not have a closed structure in an electrode region forming a lower region of the trench-type depression, the grain elements being provided such that they are grown on the inner areas of the trench-type depression selectively in the electrode region, while the amorphous silicon layer that has continued to grow is provided in the collar region of the trench-type depression.

13. Memory cell according to claim 12 , wherein the substrate is formed from a p-doped silicon material.

14. Memory cell according to claim 12 , wherein a silicon nitride material and/or an aluminum oxide material is provided in the collar region of the trench-type depression.

15. Memory cell according to claim 12 , wherein the grain elements grown on the inner areas of the trench-type depression in the electrode region have a grain size in a range of 10 nm to 80 nm.

16. Memory cell according to claim 12 , wherein the trench-type depression in the substrate has a structure width in a range of 20 nm to 500 nm.

17. Memory cell according to claim 12 , wherein grain elements grown on the inner areas of the trench-type depression in the electrode region are formed as hemispherical silicon grains.

18. Method according to claim 1 , wherein the barrier layer is produced in the electrode region of the trench-type depression by means of a non-conformal deposition.

19. Method according to claim 1 , wherein the barrier layer is produced in the electrode region of the trench-type depression by means of the following steps of:

a) filling the trench-type depression with a filling material;

b) removing the filling material in an upper region of the trench-type depression;

c) depositing the barrier layer;

d) etching anisotropically the barrier layer; and

e) removing the residual filling material.

20. Method for selectively fabricating hemispherical grain elements, having the steps of:

a) providing a substrate;

b) patterning the substrate;

c) depositing a barrier layer on the patterned substrate in such a way that both parts of the substrate and parts of the barrier layer are uncovered at the surface; and

d) depositing a silicon material in such a way that the latter grows on the substrate in the form of hemispherical grain elements, while a homogeneous layer made of the silicon material is formed on the barrier layer.

21. Method according to claim 20 , wherein the barrier layer is deposited selectively on the patterned substrate.

22. Method according to claim 20 , wherein the barrier layer is deposited over the whole area on the patterned substrate and is subsequently patterned.