IP Library Granted Patent US 7,056,802
Granted Patent B2
US 7,056,802 · App. 10/889,670 · Granted Jun 6, 2006

Method for fabricating a trench capacitor with an insulation collar which is electrically connected to a substrate on one side via a buried contact, in particular for a semiconductor memory cell

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Quick Facts
Patent No.
US 7,056,802
App. No.
10/889,670
Granted
Jun 6, 2006
Kind
B2
Abstract

The present invention provides a method for fabricating a trench capacitor with an insulation collar ( 10; 10 a, 10 b ) in a substrate ( 1 ), which is electrically connected to the substrate ( 1 ) on one side via a buried contact ( 15 a, 15 b; 70 ), having the steps of: providing a trench ( 5 ) in the substrate ( 1 ) using a hard mask ( 2, 3 ) with a corresponding mask opening; providing a capacitor dielectric ( 30 ) in the lower and central trench region, the insulation collar ( 10 ) in the central and upper trench region and an electrically conductive filling ( 20 ) in the lower and central trench region, the top side of the electrically conductive filling ( 20 ) being sunk in the upper trench region with respect to the top side of the substrate ( 1 ); providing a silicon nitride liner ( 40 ) above the hard mask ( 2, 3 ) and in the trench ( 5 ); providing a silicon liner ( 50 ) above the silicon nitride liner ( 40 ); carrying out an oblique implantation (I 1 ), as a result of which a shaded region ( 50 a ) of the silicon liner ( 50 ) is made selectively removable with respect to the rest of the silicon liner ( 50 ) by means of an etching process; selectively removing the shaded region ( 50 a ) of the silicon liner ( 50 ) by means of the etching process; oxidizing the rest of the silicon liner ( 50 ); carrying out a spacer etching at the oxidized rest of the silicon liner ( 50′ ); and depositing and etching back a conductive filling ( 70 ) in order to form the buried contact.

Claims (14)

1. Method for fabricating a trench capacitor with an insulation collar in a substrate, which is electrically connected to the substrate on one side via a buried contact, in particular for a semiconductor memory cell with a planar selection transistor that is provided in the substrate and connected via the buried contact having the steps of:

(a) providing a trench in the substrate using a hard mask with a corresponding mask opening;

(b) providing a capacitor dielectric in the lower and central trench region, the insulation collar in the central and upper trench region and an electrically conductive filling in the lower and central trench region, the top side of the electrically conductive filling being sunk in the upper trench region with respect to the top side of the substrate;

(c) providing a silicon nitride liner above the hard mask and in the trench;

(d) providing a silicon liner above the silicon nitride liner;

(e) carrying out an oblique implantation, as a result of which a shaded region of the silicon liner is made selectively removable with respect to the rest of the silicon liner by means of an etching process;

(f) selectively removing the shaded region of the silicon liner by means of the etching process;

(g) oxidizing the rest of the silicon liner;

(h) carrying out a spacer etching at the oxidized rest of the silicon liner; and

(i) depositing and etching back a conductive filling in order to form the buried contact.

2. Method according to claim 1 , wherein, after carrying out the spacer etching, that part of the silicon nitride liner which is not covered by the oxidized rest of the silicon liner is removed and a further silicon nitride liner is subsequently deposited.

3. Method according to claim 1 wherein the capacitor dielectric is also provided and left in the upper trench region below the silicon nitride liner.

4. Method according to claim 1 , wherein the implantation is carried out using boron ions or boron fluoride ions or other ions and the etching process is an alkaline etching, in particular an NH 4 OH etching.

5. Method according to claim 1 , wherein the insulation collar is incorporated into the substrate.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 16, 2015
From: INFINEON TECHNOLOGIES AG
To: POLARIS INNOVATIONS LIMITED
Reel/Frame 036877/0513 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 8, 2015
From: QIMONDA AG
To: INFINEON TECHNOLOGIES AG
Reel/Frame 035623/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2010
From: INFINEON TECHNOLOGIES AG
To: QIMONDA AG
Reel/Frame 023853/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2004
From: GOLDBACH, MATTHIAS
To: INFINEON TECHNOLOGIES AG
Reel/Frame 015089/0625 →