Method and apparatus for producing a reference voltage

1. A method for producing a reference voltage comprising:

transmitting a data signal to a first receiver;

transmitting a clock signal to a second receiver;

discriminating the clock signal with the reference voltage at the second receiver to produce an output clock signal;

integrating the output clock signal on an output side of the second receiver to produce an integrated value;

producing the reference voltage from the integrated value in order to level-discriminate between logic states of the data signal; and

applying the reference voltage to reference voltage inputs on the first and second receivers.

2. The method of claim 1 , wherein the integrated value is compared, before being applied to the reference voltage inputs, with a reference-ground voltage that is produced by halving a supply voltage for the first and second receivers.

3. The method of claim 1 , wherein the received clock signal is a continuous signal train of low and high signal states.

4. The method of claim 3 , wherein the received clock signal has the same low and high voltage levels as a received data signal.

5. The method of claim 3 , wherein the received clock signal is subject to the same system-related variations at the receiver end as the received data signal.

6. The method of claim 1 , wherein the clock signal is driven by the same type of driver amplifiers as the data signal.

7. The method of claim 1 , wherein the clock signal is integrated during a particular period of time before the data signal is received.

8. The method of claim 1 , wherein the data strobe signal in the case of data transmission to and from DDR-DRAM chips is used as the clock signal.

9. The method of claim 8 , wherein the received data signal is integrated at least on every DDR-DRAM chip.

10. The method of claim 9 , wherein the data signal is additionally integrated in a memory controller chip which receives the data.

11. An apparatus for producing a reference voltage that is applied to reference voltage inputs on first and second receiver units in a receiver end in order to level-discriminate between logic states of a data signal in the case of the first receiver unit, and a clock signal in the case of the second receiver unit, both sinals transmitted to the receiver end, the apparatus comprising:

a transmission device for transmitting the data signal and thee clock signal to the receiver end;

an integrator in the receiver end that integrates the level-discriminated clock signal and produces the reference voltage from the integrated value; and

wherein the integrator is provided on an output side of the second receiver unit, which receives the clock signal.

12. The apparatus of claim 11 , wherein a feedback loop routed from an output of the integrator to the reference voltage inputs of the first and second receiver units contains a comparator that compares the integrated value with a reference-ground voltage produced by halving the supply voltage level for the receiver units.

13. The apparatus of claim 12 , wherein the transmitted clock signal has a continuous succession of low and high clock signal states of respectively equal duration and constant period.

14. The apparatus of claim 13 , wherein the transmitted clock signal has the same low and high voltage levels at the receiver end as a received data signal and is subject to the same system-related variations as the received data signal.

15. The apparatus of claims 14 used for producing the reference voltage for the data reception of data transmitted between DDR-DRAM chips, wherein the transmitted clock signal is a data strobe signal.

16. The apparatus of claim 15 , wherein the integrator integrates the level-discriminated data strobe signal during a particular period of time before the data signal is received.

17. An apparatus for level-discriminating between logic states of a data signal and a clock signal both transmitted to a receiver, the apparatus comprising:

a first receiver unit in the receiver end having a first and a second input, the first input receiving the data signal and the second input receiving a reference voltage to level-discriminate between logic states of the received data signal;

a second receiver unit in the receiver end having a first and a second input and an output, the first input receiving the clock signal, the second input receiving the reference voltage to level-discriminate between logic states of the received clock signal and the output producing an output signal;

an integrator coupled to the output of the second receiver unit such that it integrates the output signal and produces an integrated value therefrom; and

wherein the reference voltage is produced from the integrated value.

18. The apparatus of claim 17 , wherein a feedback loop routed from an output of the integrator to the second input of the first and second receiver units contains a comparator that compares the integrated value with a reference-round voltage produced by halving the supply voltage level for the receiver units.

19. The apparatus of claim 18 , wherein the transmitted clock signal has a continuous succession of low and high clock signal states of respectively equal duration and constant period.

20. The apparatus of claim 19 , wherein the transmitted clock signal has the same low and high voltage levels at the receiver end as a received data signal and is subject to the same system-related variations as the received data signal.

21. The apparatus of claim 17 , wherein the integrator integrates the output signal of the second receiver unit during a particular period of time before the data signal is received.