Control system for a dynamic random access memory and method of operation thereof

1. A method of operating a dynamic random access memory (DRAM) device that includes memory cells organized in a plurality of blocks, the method comprising:

storing data in a first block of memory cells, the data being stored in the first block in a single cell mode; and

storing data in a second block of memory cells, the data being stored in the second block in a twin cell mode, wherein the second block stores data in the twin cell mode at the same time the first block stores data in the twin cell mode.

2. The method of claim 1 , further comprising performing a refresh operation, wherein the reference operation refreshes cells of the first block at a first refresh rate and refreshes cells of the second block at a second refresh rate that is longer than the first refresh rate.

3. The method of claim 1 , further comprising:

storing data in a third block of memory cells, the data being stored in the third block in a first mode; and

transitioning the third block to store the data in a second mode, wherein the first mode comprises one of the single cell mode or the twin cell mode and the second mode comprises the other of the single cell mode or the twin cell mode.

4. A method of operating a dynamic random access memory device, the method comprising:

providing an array of dynamic random access memory cells arranged in a plurality of blocks; and

storing data in ones of the blocks of memory cells, wherein the data is stored in either a single cell mode or a twin cell mode as a function of the block.

5. The method of claim 4 , further comprising receiving mode information, the mode information determining whether a particular block of the plurality of blocks stores data in the single cell mode or the twin cell mode.

6. The method of claim 5 , wherein the mode information is received from an external controller.

7. The method of claim 5 , wherein the mode information is determined by circuitry on-chip with the array of dynamic random access memory cells.

8. The method of claim 4 , wherein storing data in ones of the blocks of memory cells comprises operating in an adaptive mode in which the device selects a mode of operation based upon address-locations of accesses that are requested.

9. The method of claim 4 , wherein, during a sleep mode, each of the blocks of memory cells is operated in the twin cell mode.

10. A method of operating a digital recording device, the method comprising:

recording a digital image;

storing the recorded digital image in a dynamic random access memory, the recorded digital image being stored in a single cell mode;

processing the recorded digital image; and

storing the processed digital image in the dynamic random access memory, the processed digital image being stored in a twin cell mode.

11. The method of claim 10 , wherein storing the recorded digital image comprises transferring data from a charge-coupled device to the dynamic random access memory in an uncompressed fashion.

12. The method of claim 10 , further comprising transmitting the processed digital image from the dynamic random access memory.

13. The method of claim 12 , further comprising causing the dynamic random access memory to transition from the twin cell mode to the single cell mode prior to transmitting the processed digital image.

14. The method of claim 10 , wherein, prior to recording the digital image, the method further comprises:

receiving an indication that an image is to be recorded; and

causing the dynamic random access memory to transition from the twin cell mode to the single cell mode.

15. The method of claim 10 , wherein storing the recorded digital image in the dynamic random access memory comprises storing the recorded digital image in a portion of the dynamic random access memory, wherein the recorded digital image is stored in the single cell mode while other portions of the dynamic random access memory store data in the twin cell mode.