Method for fabricating a gate structure of a FET and gate structure of a FET
View Patent ↗A method for fabricating a gate structure of a FET, having: (a) deposition and patterning of a sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section; (b) implantation of a channel doping into the gate section; (c) deposition and patterning of spacers at the sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers; (d) introduction of a mask material into the gate section that is not covered by the spacers; (e) removal of the spacers selectively with respect to the sacrificial layer sequence and mask material); (f) implantation of a halo doping in regions uncovered by the removed spacers; (g) removal of the mask material; (h) formation of a gate on the gate section; and (j) removal of the sacrificial layer sequence selectively with respect to the gate.
1. A method for fabricating a gate structure of a FET, comprising:
depositing and pattering of sacrificial layer sequence on a semiconductor substrate and uncovering of a gate section;
implanting a channel doping into the gate section;
depositing and patterning of spacers at sidewalls of the sacrificial layer sequence with the formation of a gate section that is not covered by the spacers;
introducing of a mask material into the gate section that is not covered by the spacers;
removing the spacers selectively with respect to the sacrificial layer sequence and mask material;
implanting a halo doping in regions uncovered by the removed spacers;
removing the mask material;
forming a gate on the gate section; and
removing the sacrificial layer sequence selectively with respect to the gate.
2. The method according to claim 1 , wherein the sacrificial layer is taken from a group consisting of a sacrificial oxide, polysilicon and silicon nitride Si 3 N 4 .
3. The method according to claim 1 , wherein an oxide is formed at least on sidewall sections of the sacrificial layer sequence.
4. The method according to claim 1 , wherein, for the deposition and patterning of the spacers, a layer is deposited conformally, which layer is etched back anisotropically selectively nitride.
5. The method according to claim 1 , wherein, for the introduction of the mask material, the mask material is deposited and subsequently etched back or planarized by means of a CMP process.
6. The method according to claim 1 , wherein the mask material is etched selectively and serves as an etching mask during an etching of the polysilicon.
7. The method according to claim 1 , wherein, before the deposition of the gate material, a gate oxide is grown in the gate region uncovered by the spacers and the mask material.
8. The method according to claim 1 , wherein, before the growth of a gate oxide, a sacrificial oxide is removed in the gate section.
9. The method according to claim 1 , wherein polysilicon or TiN/W is deposited as the gate material.
10. The method according to claim 1 , wherein, after the deposition of the gate a planarization step is carried out.