Self-aligned V0-contact for cell size reduction
An FeRAM comprising includes a ferroelectric material sandwiched between a top electrode and a bottom electrode. A V0-contact provides an electrical connection with an underlying CS-contact. The V0-contact is aligned using the bottom electrode. A liner layer covers a sidewall of the bottom electrode and provides a stop to an etch a hole forming the V0-contact. A method is utilized to form a V0-contact in an FeRAM comprising. An Fe capacitor of the FeRAM is encapsulated, a bottom electrode is etched, a liner layer is deposited covering a sidewall of the bottom electrode, and a hole is etched for the V0-contact until the etching is stopped by the liner layer.
1. A method for forming a V0-contact in a ferroelectric random access memory (FeRAM) comprising:
encapsulating ferroelectric capacitor of the FeRAM;
etching a bottom electrode;
depositing a liner layer covering a sidewall of the bottom electrode; and
etching a hole in which the V0-contact is formed until the etching is stopped by the liner layer.
2. The method of claim 1 , further comprising the step of depositing an Alumina spacer on walls of the hole following etching of the hole.
3. The method of claim 1 , further comprising the step of performing a break-through etch to clean the bottom of the V0-contact hole so that the V0-contact can electrically connect to an underlying source/drain (CS) contact.
4. A method for forming a V0-contact in a ferroelectric random access memory (FeRAM) comprising:
providing a liner layer on at least a sidewall of a bottom electrode of a ferroelectric capacitor of the FeRAM;
providing a dielectric layer over at least the ferroelectric capacitor and/or the liner layer, and
etching a hole in the dielectric layer for the V0-contact directly adjacent to and/or partially overlying the ferroelectric capacitor, wherein etching of the bottom electrode is prevented by the liner layer.
5. The method claimed in claim 4 further comprising providing an Alumina spacer on a wall of the hole.
6. The method claimed in claim 5 wherein the wall comprises the dielectric layer and the liner layer.
7. The method claimed in claim 4 further comprising break-through etching the bottom of the V0-contact hole and/or the liner layer.
8. The method claimed in claim 7 further comprising depositing a V0-contact in the hole which can electrically connect to a source/drain (CS) contact underneath the bottom of the V0-contact hole.
9. The method claimed in claim 4 wherein the side wall is substantially vertical and is formed by etching the bottom electrode.
10. The method claimed in claim 9 wherein etching the bottom electrode further comprises forming a mask over the bottom electrode and wherein the liner layer is also provided on the mask.