Fabrication method for semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently
View Patent ↗The present invention provides a fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently. A fabrication of a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region, is followed by a deposition of a cover layer that grows over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region. This is followed by a fabrication of the patterned second region, the patterned first region remaining protected at least by the closure of the cover layer. The final step effected is a removal of the cover layer above the semiconductor structure, which now has two differently patterned regions.
1. A fabrication method for a semiconductor structure in a substrate, the semiconductor structure having at least two regions that are to be patterned differently, comprising:
(a) fabricating a patterned first region in the substrate, so that the semiconductor structure has a non-patterned second region and the patterned first region;
(b1) depositing a cover layer on horizontal planes of the semiconductor structure, the cover layer growing over the patterned first region, so that the cover layer above the patterned first region forms a closure, which covers over the patterned first region without completely filling the first region, and forms a horizontal surface above the semiconductor structure;
(b2) providing a first barrier layer above the horizontal surface of the cover layer;
(b3) providing a second barrier layer above the first barrier layer;
(b4) providing a structure by means of a first mask for an unpatterned second region above the semiconductor structure;
(b5) transferring the structure into the second barrier layer, so that the regions of the second barrier layer that are to be removed on account of the structure are selectively removed for the formation of a process window;
(b6) transferring the structure into the first barrier layer, so that the regions of the first barrier layer that are to be removed on account of the structure are selectively removed for the further formation of the process window;
(b7) transferring the structure into the cover layer, so that the regions of the cover layer that are to be removed on account of the structure are selectively removed, thereby further forming the process window for the further patterning of the second region; and
(c1) fabricating the patterned second region in the process window, the patterned first region remaining protected at least by the cover layer; and
(d) removing the cover layer above the semiconductor structure which has the two differently patterned regions.
2. The method according to claim 1 , wherein the cover layer is a carbon hard mask.
3. The method according to claim 2 , wherein the carbon hard mask is deposited by means of a plasma-chemical vapor deposition process, the process parameters being determined with 200 to 1000 sccm for the C 3 H 6 flowrate, 3000 to 20000 sccm for the He flowrate, 3.5 to 10 torr for the process pressure and 800 to 3000 watts for the radiofrequency energy.
4. The method according to claim 1 , wherein the first barrier layer is an SiON layer.
5. The method according to claim 1 , wherein the second barrier layer is a photosensitive resist.
6. The method according to claim 1 , wherein the first mask is a photomask.
7. The method according to claim 1 , wherein the first patterned region, according to (a) forms an electrical contact of a bit line of a DRAM memory cell within the substrate.
8. The method according to claim 7 , wherein the electrical contact of a bit line is led through two word lines of the DRAM memory cells, the word lines being insulated by means of a respective silicon nitride.
9. The method according to claim 1 , wherein the second patterned region forms a CS contact of a DRAM memory cell.
10. The method according to claim 9 , wherein a borophosphosilicate glass is provided as insulating layer between the CS contact and the contact of the bit line of the DRAM memory cell.
11. The method according to claim 4 , wherein according to (b6) the SiON layer is etched back by means of an anisotropic, fluorine-based process for formation of the process window.
12. The method according to claim 2 , wherein the selective removal of the carbon hard mask, according to (b7), is an anisotropic dry etching using an oxygen plasma, an entire photo-sensitive resist being removed above the semiconductor structure.
13. The method according to claim 10 , wherein according to (b7), the borophosphosilicate glass is etched back in the process window by means of an anisotropic fluorine-based process, the first barrier layer being removed above the semiconductor structure.
14. The method according to claim 2 , wherein the removal of the carbon hard mask, according to (d), is an isotropic dry etching using an oxygen plasma.