Method for operating an electrical writable and erasable memory cell and a memory device for electrical memories

1. A method for operating an electrically writable and erasable memory cell, which has a channel region being operated in a first and a second direction, the memory cell characterized by at least one effective parameter, the method comprising:

storing information in the memory cell, wherein information is stored as the difference between the effective parameter in operation of the channel region in the first direction and the effective parameter in operation of the channel region in the second direction; and

retrieving the stored information from the memory cell.

2. The method according to claim 1 , wherein two sets of information are distinguished by the direction of operation of the channel region when the effective parameter of the channel region in the first direction is higher than the effective parameter in operation of the channel region in the second direction, wherein the magnitude of the effective parameter difference is the same in each direction.

3. The method according to claim 2 , wherein the memory cell includes a memory cell transistor having a threshold voltage and wherein the effective parameter is the threshold voltage of a memory cell transistor.

4. The method according to claim 3 , wherein the threshold voltage is stipulated within a pre-determined voltage range.

5. The method according to claim 4 , wherein further information is stipulated within further pre-determined voltage ranges.

6. A memory device for electrically readable and erasable information memories, the memory device comprising:

a memory cell field with at least one memory cell that has a channel region between a drain region and a source region, the channel region being bi-directionally operable, the memory cell further including a storage area that is adjustable such that an effective parameter of the memory cell when operating the channel region in a first direction is different than the effective parameter of the memory cell when operating the channel region in the second direction; and

a reading device operatively coupled to the memory cell, the reading device operable to determine the difference of the effective parameter of the memory cell when operating the channel region in the first direction and the effective parameter of the memory cell when operating the channel region in the second direction and determine a programming state based upon that difference.

7. The memory device according to claim 6 , further comprising a writing device that adjusts the storage urea such that information to be stored is converted into a threshold voltage difference of the channel region.

8. The memory device according to claim 7 , wherein the information to be stored comprises one bit.

9. The memory device according to claim 8 , wherein the memory cell is an NROM memory cell element.

10. The memory device according to claim 9 , wherein the memory cell includes a first oxide layer adjacent the channel region, a nitride layer adjacent the first oxide layer, and a second oxide layer adjacent the nitride layer.

11. The memory device according to claim 9 , wherein the storage area of the memory cell comprises a local charge storage means.