Method for fabricating a semiconductor structure
View Patent ↗A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.
1. Method for fabricating a semiconductor structure having a plurality of memory cells which are provided in a semiconductor substrate (l) of a first conduction type (p) and comprise a plurality of planar selection transistors and a corresponding plurality of storage capacitors (TK 1 -TK 4 ; TK 1 ′-TK 4 ′) connected thereto, the selection transistors having respective first and second active regions ( 60 , 61 ; 62 , 61 ; 63 , 64 ; 65 , 64 ; 60 ′, 61 ′; 62 ′, 63 ′; 64 ′, 65 ′; 66 ′, 67 ′) of the second conduction type (n), of which the first active regions ( 60 , 62 , 63 , 65 ) are connected to the storage capacitors (TK 1 -TK 4 ; TKl′-TK 4 ′) and the second active regions ( 61 , 64 , 6 l′, 63 ′, 65 ′, 67 ′) are connected to respective bit lines, and respective gate stacks (GS 1 -GS 8 ), which are provided above the semiconductor substrate ( 1 ) in a manner insulated by a gate dielectric ( 5 ), having the following steps:
providing the storage capacitors (TK 1 -TK 4 ; TK 1 ′-TK 4 ′) in the semiconductor substrate ( 1 );
providing the gate dielectric ( 5 ) above the semiconductor substrate ( 1 );
providing the gate stacks (GS 1 -GS 8 ) on the gate dielectric ( 5 )
carrying out a first introduction step (I 1 , I 2 ; I 1 ″) for introducing first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) of the first conduction type (p) in a self-aligned manner with respect to edges of the gate stacks (GS 1 -GS 8 ) on the side of the second active regions ( 61 , 64 , 61 ′, 63 ′, 65 ′, 67 ′) for the purpose of increasing the doping of a channel region of the selection transistors which is spaced apart from the first active regions ( 60 , 62 , 63 , 65 );
carrying out a second introduction step (I 1 ′, I 2 ′; I 1 ′″) for introducing second doping regions ( 101 , 106 , 111 , 121 , 131 ; 106 ″, 111 ″, 121 ″, 131 ″, 141 ″), which counteract a thermal outdiffusion of the first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) in the direction of the first active regions ( 60 , 62 , 63 , 65 );
providing the first and second active regions ( 60 , 61 ; 62 , 61 ; 63 , 64 ; 65 , 64 ; 60 ′, 61 ′; 62 ′, 63 ′; 64 ′, 65 ′; 66 ′, 67 ′) in a self-aligned manner with respect to edges of the gate stacks (GS 1 -GS 8 ).
2. Method according to claim 1 ,
characterized
in that the first introduction step (I 1 , I 2 ; I 1 ″) and/or the second introduction step (I 1 ′, I 2 ′; I 1 ′″) are implantation steps.
3. Method according to claim 1 or 2 ,
characterized
in that the first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) are boron regions and the second doping regions ( 101 , 106 , 111 , 121 , 131 ; 106 ″, 111 ″, 121 ″, 131 ″, 141 ″) are nitrogen or carbon regions.
4. Method according to claim 1 , 2 or 3 ,
characterized
in that a plurality of second introduction steps (I 1 ′, I 21 ′I 1 ′″) for introducing second doping regions ( 101 , 106 , 111 , 121 , 131 ; 106 ′, 111 ″, 121 ″, 131 ″, 141 ″) which counteract a thermal outdiffusion of the first doping regions ( 100 , 105 , 110 , 120 , 130 ; 105 ″, 110 ″, 120 ″, 130 ″, 140 ″) in the direction of the first active regions ( 60 , 62 , 63 , 65 ), are carried out, preferably as implantation steps.
5. Method according to one off the preceding claims,
characterized
in that a sidewall oxide ( 40 ) is formed on uncovered sidewalls of the gate stacks (GS 1 -GS 8 ) with diffused first and second doping regions simultaneously being formed below the gate edge.
6. Method according to one of the preceding claims,
characterized
in that the gate stacks (GS 1 -GS 8 ) are applied approximately equidistantly with respect to one another, a storage capacitor (TK 1 ′, TK 2 ′, TK 3 ′, TK 4 ′) being arranged below every second adjacent gate stack GS 1 , GS 3 , GS 5 , GS 7 ) in the semiconductor substrate ( 1 ).
7. Method according to one of the preceding claims 1 to 5 ,
characterized
in that the gate stacks (GS 1 -GS 8 ) are applied approximately equidistantly with respect to one another, a storage capacitor (TK 1 , TK 2 , TK 3 , TK 4 ) being arranged alternately below every third or first adjacent gate stack (GS 1 , GS 4 , GS 5 , GS 8 ) in the semiconductor substrate ( 1 ).
8. Method according to one of the preceding claims,
characterized
in that diffused first and second doping regions are formed by means of a separate heat treatment step set in a predetermined manner.
9. Method according to one of the preceding claims,
characterized
in that the gate stacks (GS 1 -GS 8 ) are fabricated with a linear spacing of less than 100 nm.
10. Method according to one of the preceding claims,
characterized
in that the gate stacks (GS 1 -GS 8 ) are provided in a parallel, striptype manner on the semiconductor substrate ( 1 ).