Fabrication method for a semiconductor structure having integrated capacitors
View Patent ↗The present invention provides a fabrication method for a semiconductor structure having integrated capacitors and a corresponding semiconductor structure. The fabrication method has the following steps of: providing a semiconductor substrate ( 1; 1′, 60, 1 ″) having a front side (VS) and a rear side (RS); providing trenches ( 5 ) in the semiconductor substrate ( 1; 1′, 60, 1 ″) proceeding from the front side (VS) of the semiconductor substrate ( 1; 1′, 60, 1 ″); providing a respective inner capacitor electrode ( 6 ) in the trenches ( 5 ); uncovering the inner capacitor electrodes ( 6 ) proceeding from the rear side (RS) of the semiconductor substrate ( 1; 1′, 60, 1 ″); providing a capacitor dielectric ( 40 ) on the uncovered inner capacitor electrodes ( 6 ); and providing outer capacitor electrodes ( 50 ) on the capacitor dielectric ( 40 ) on the inner capacitor electrodes ( 6 ).
1. Fabrication method for a semiconductor structure having integrated capacitors, having the steps of:
(a) providing a semiconductor substrate having a front side and a rear side;
(b) providing trenches in the semiconductor substrate proceeding from the front side of the semiconductor substrate;
(c) providing a respective inner capacitor electrode in the trenches;
(d) uncovering the inner capacitor electrodes proceeding from the rear side of the semiconductor substrate;
(e) providing a capacitor dielectric on the uncovered inner capacitor electrodes; and
(f) providing outer capacitor electrodes on the capacitor dielectric on the inner capacitor electrodes.
2. Method according to claim 1 , wherein the inner capacitor electrodes cover the respective trench on the trench walls and leave a cavity in the trench.
3. Method according to claim 2 , wherein the following steps are performed for uncovering the inner capacitor electrodes:
(a) providing an etching stop layer on the trench walls under the inner capacitor electrodes;
(b) removing the semiconductor substrate, the etching stop layer and the inner capacitor electrodes on the rear side for the purpose of opening the cavity;
(c) providing a first filling layer in the cavity;
(d) sinking the first filling layer and the respective inner capacitor electrode in the cavity;
(e) providing a second filling layer on the rear side, which plugs the trenches;
(f) removing the second filling layer for the purpose of the semiconductor substrate on the rear side between the trenches;
(g) removing selectively the semiconductor substrate on the rear side as far as the upper trench region with respect to the etching stop layer and the second filling layer; and
(h) removing the etching stop layer and the first and second filling layers.
4. Method according to claim 2 wherein the following steps are performed for uncovering the inner capacitor electrodes:
(a) providing an etching stop layer on the trench walls under the inner capacitor electrodes;
(b) removing selectively the semiconductor substrate on the rear side as far as the upper trench region with respect to the etching stop layer;
(c) providing a third filling layer for embedding the trenches;
(d) removing the third filling layer, the etching stop layer and the inner capacitor electrodes on the rear side for the purpose of opening the cavity; and
(e) removing the etching stop layer and the third filling layer.
5. Method according to claim 2 wherein the following steps are performed for uncovering the inner capacitor electrodes:
(a) providing an etching stop layer on the trench walls under the inner capacitor electrodes;
(b) removing selectively the semiconductor substrate on the rear side as far as the upper trench region with respect to the etching stop layer; and
(c) removing the etching stop layer.
6. Method according to claim 1 , wherein the semiconductor substrate has a rear-side first substrate layer, a front-side second substrate layer and a middle insulation layer, the middle insulation layer functioning as an etching stop in the course of uncovering the inner capacitor electrodes.
7. Method according to claim 1 , wherein the inner capacitor electrodes fill the respective trench.
8. Method according to claim 5 , wherein the following steps are performed for uncovering the inner capacitor electrodes:
(a) providing an etching stop layer on the trench walls under the inner capacitor electrodes;
(b) removing the semiconductor substrate, the etching stop layer and the inner capacitor electrodes on the rear side for the purpose of opening the filled trenches;
(c) sinking the inner capacitor electrodes;
(d) providing a fourth filling layer on the rear side, which plugs the trenches;
(e) removing selectively the semiconductor substrate on the rear side as far as the upper trench region with respect to the etching stop layer; and
(f) removing the etching stop layer.
9. Method according to claim 1 , wherein the trenches are widened in bottle-shaped fashion in the lower trench region.
10. Method according to claim 1 , wherein the outer capacitor electrodes are provided from a whole-area conductive layer on the rear side.