Electronic memory apparatus, and method for deactivating redundant bit lines or word lines

1. Electronic memory apparatus for storing data, having:

a) a memory cell array which has memory cells arranged in rows and columns;

b) a column address decoding unit for decoding a column addressing signal and for actuating an addressed bit line in the memory cell array;

c) a column redundancy activation unit for activating a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus;

d) a row address decoding unit for decoding a row addressing signal and for actuating an addressed word line in the memory cell array; and

e) a row redundancy activation unit for activating a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus,

wherein the electronic memory apparatus also has:

f) a column deactivation unit for deactivating unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus; and

g) a row deactivation unit for deactivating unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus.

2. Apparatus according to claim 1 , wherein the column deactivation unit for deactivating bit lines and/or the row deactivation unit for deactivating word lines are integrated together with the memory cell array.

3. Method for electronically storing data in a memory apparatus which has a memory cell array having memory cells arranged in rows and columns, having the following steps:

a) using a column address decoding unit to decode a column addressing signal, and an addressed bit line in the memory cell array is actuated using the decoded column addressing signal;

b) using a column redundancy activation unit to activate a redundant bit line when a currently used bit line has been determined to be faulty during testing of the memory apparatus;

c) using a row address decoding unit to decode a row addressing signal, and an addressed word line in the memory cell array is actuated using the decoded row addressing signal;

d) using a row redundancy activation unit to activate a redundant word line when a currently used word line has been determined to be faulty during testing of the memory apparatus,

wherein the method also has the following steps:

e) deactivating unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus using a column deactivation unit; and

f) deactivating unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus using a row deactivation unit.

4. Method according to claim 3 , wherein the unused, redundant bit lines and those bit lines which have been determined to be faulty during testing of the memory apparatus are automatically placed at a predetermined potential using the column deactivation unit.

5. Method according to claim 3 , wherein the unused, redundant word lines and those word lines which have been determined to be faulty during testing of the memory apparatus are automatically placed at a predetermined potential using the row deactivation unit.

6. Method according to claim 3 , wherein a bit line is also deactivated using the column deactivation unit when a fault occurs in a memory cell area of the memory cell array which is associated with the bit line.

7. Method according to claim 3 , wherein a word line is also deactivated using the row deactivation unit when a fault occurs in a memory cell area of the memory cell array which is associated with the word line.