Duty cycle correction
View Patent ↗A duty cycle correction circuit comprises an averaging circuit configured to receive a first signal and a second signal and provide a third signal, a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal, and a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.
1. A duty cycle correction circuit comprising:
an averaging circuit configured to receive a first signal and a second signal and provide a third signal;
a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal; and
a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal.
2. The duty cycle correction circuit of claim 1 , wherein the duty cycle of the fifth signal is 50%.
3. The duty cycle correction circuit of claim 1 , wherein the first signal comprises a clock signal.
4. The duty cycle correction circuit of claim 1 , wherein the fourth signal comprises an inverted clock signal.
5. The duty cycle correction circuit of claim 1 , wherein the first signal has a first edge and the second signal has a second edge and the averaging circuit is configured to provide a third edge of the third signal between the first edge and the second edge.
6. The duty cycle correction circuit of claim 5 , wherein the third edge is halfway between the first edge and the second edge.
7. The duty cycle correction circuit of claim 5 , wherein the first edge is a rising edge, the second edge is a rising edge, and the third edge is a rising edge.
8. The duty cycle correction circuit of claim 1 , wherein the third signal has a first edge and the fourth signal has a second edge and the duty restoration circuit is configured to provide the fifth signal having a logic high time equal to a time between the first edge and the second edge.
9. The duty cycle correction circuit of claim 8 , wherein the first edge is a rising edge and the second edge is a rising edge.
10. The duty cycle correction circuit of claim 1 , wherein the fifth signal has a falling edge and the synchronous mirror delay circuit is configured to receive a delayed fifth signal having a rising edge and provide the second signal having a rising edge at a time after the falling edge of the fifth signal equal to a time between the rising edge of the delayed fifth signal and the falling edge of the fifth signal.
11. A method for correcting the duty cycle of a clock signal, the method comprising:
averaging a clock signal and a second signal to provide a third signal;
generating a corrected clock signal having a duty cycle closer to 50% than the clock signal based on the third signal and an inverted clock signal; and
synchronous mirror delaying the corrected clock signal to provide the second signal.
12. The method of claim 11 , wherein generating the corrected clock signal comprises generating the corrected clock signal having a duty cycle of 50%.
13. The method of claim 11 , wherein the clock signal has a first edge and the second signal has a second edge and averaging the clock signal and the second signal comprises providing a third edge of the third signal between the first edge and the second edge.
14. The method of claim 11 , wherein the third signal has a first edge and the fourth signal has a second edge and generating the corrected clock signal comprises providing the corrected clock signal having a logic high time equal to a time between the first edge and the second edge.
15. The method of claim 11 , wherein the corrected clock signal has a falling edge and synchronous mirror delaying the corrected clock signal comprises receiving a delayed corrected clock signal having a rising edge and providing the second signal having a rising edge at a time after the falling edge of the corrected clock signal equal to a time between the rising edge of the delayed corrected clock signal and the falling edge of the corrected clock signal.
16. A memory system comprising:
a duty cycle correction circuit comprising:
an averaging circuit configured to receive a first signal and a second signal and provide a third signal;
a duty restoration circuit configured to receive the third signal and a fourth signal and provide a fifth signal having a duty cycle closer to 50% than the first signal; and
a synchronous mirror delay circuit configured to receive the fifth signal and provide the second signal; and
a memory circuit configured to receive the fifth signal and one of store and retrieve data.
17. The memory system of claim 16 , wherein the duty cycle correction circuit and the memory circuit are a single semiconductor chip.
18. The memory system of claim 16 , wherein the memory circuit comprises a dynamic random access memory.
19. The memory system of claim 16 , wherein the memory circuit comprises a synchronous dynamic random access memory.
20. The memory system of claim 16 , wherein the memory circuit comprises a double data rate synchronous dynamic random access memory.