Semiconductor chip with metallization levels, and a method for formation in interconnect structures
View Patent ↗A metallization surface ( 5 ), which acts as an etching stop layer during the production of openings ( 4 ) in a passivation layer ( 3 ) applied to its upper face and protects an interconnect structure ( 6 ) arranged underneath it, is arranged in an uppermost metallization level ( 1 ). A further opening is produced in the metal surface ( 5 ), through which a focused ion beam is aimed at the interconnect structure ( 6 ) in order to connect interconnects to one another and/or to interrupt at least one interconnect. The wiring of the integrated circuit can thus be varied individually, starting from identically produced semiconductor chips.
1. A method of providing a selected one of two different electrical circuits from a single semiconductor chip comprising:
providing a semiconductor chip having formed therein a first one of said two different electrical circuits, said provided semiconductor chip comprising at least an upper metallization layer and a lower metallization layer supported by an insulating layer, said upper metallization layer defining an aperture there through and said lower metallization layer defining an interconnect structure including at least one of a conductive line for providing an electrical connection, or a pair of adjacent conductive lines electrically isolated from each other directly below said aperture in said upper metallization layer, said semiconductor top further comprising a passivation layer formed over said upper metallization layer and defining an opening therein, said opening above a portion of said upper metallization layer defining said aperture; and
directing a FIB at said at least one of said conductive lines or said pair of adjacent conductive lines;
selectively melting a portion of said at least one of said conductive line to interrupt said electrical connection or melting portions of said pair of adjacent conductive lines to form an electrical connection therebetween.
2. The method of claim 1 , further comprising forming vertical electrical connections that electrically couple the interconnect structure to one or more additional metallization levels above or below the interconnect structure.
3. The method of claim 1 , wherein said conductive line is melted such that said electrical connection is interrupted.
4. The method of claim 1 , wherein said pair of adjacent conductive lines is melted such that an electrical connection is formed between said pair.
5. The method of claim 4 , wherein said conductive line is melted such that said electrical connection is interrupted.