Clock signal synchronizing device, and clock signal synchronizing method
View Patent ↗The invention relates to a clock signal synchronizing method, and to a clock signal synchronizing device ( 101 ) to be used with the synchronization of clock signals (CLK, DQS), comprising: a delay means ( 102 ) with a variably controllable delay time (t var ), in which a clock signal (CLK) or a signal obtained therefrom is input, is loaded with the variably controllable delay time (t var ), and is output as delayed clock signal, a phase comparator ( 104 ) for comparing the phase of the clock signal (CLK) or of the signal obtained therefrom with the phase of the delayed clock signal or of a signal obtained therefrom (DCLK, FB), characterized in that additionally a means ( 401, 116 ) is provided for activating and/or deactivating said clock signal synchronizing device ( 101 ) as a function of control signals (RD) evaluated by an evaluating means ( 402 ).
1. A clock signal synchronizing device to be used with a synchronization of clock signals, comprising:
a first delay means with a variably controllable delay time, in which a clock signal or a signal obtained therefrom is input, is loaded with the variably controllable delay time, and is output as a delayed clock signal;
a second delay means with a first constant delay time, the first constant delay time chosen based on a delay caused during evaluation of control signals by an evaluating means; and
a phase comparator for comparing a phase of the clock signal or of the signal obtained therefrom with a phase of the delayed clock signal or of a signal obtained therefrom,
wherein additionally a means is provided for activating and/or deactivating said clock signal synchronizing device as a function of the control signals evaluated by the evaluating means.
2. The clock signal synchronizing device according to claim 1 , said device being provided on a memory device.
3. The clock signal synchronizing device according to claim 2 , wherein said control signals are read control signals input in the memory device.
4. The clock signal synchronizing device according to claim 1 , further comprising a third delay means with a second constant delay time.
5. The clock signal synchronizing device according to claim 4 , wherein said second constant delay time is chosen based on signal delays caused by a receiver and/or an off-chip driver.
6. The clock signal synchronizing device according to claim 1 , wherein, in addition to the delayed clock signal output by said first delay means or the signal obtained therefrom and a signal output by said second delay means or a signal obtained therefrom, are used for generating a synchronized signal output by said clock signal synchronizing device.
7. The clock signal synchronizing device according to claim 1 , wherein said device is provided in mobile end equipment comprising a mobile phone or a laptop.
8. A clock signal synchronizing method using the clock signal synchronizing device according to claim 1 , said method comprising loading a clock signal or a signal obtained therefrom with a variably controllable delay time, so that a delayed clock signal is obtained, wherein the loading is only performed if it is detected that a corresponding control signal is present at an input of said clock signal synchronizing device, or at an input of a device for which said clock signal synchronizing device is used.
9. A clock signal synchronizing device comprising:
a first delay element coupled to a clock input the first delay element comprising a controllable variable delay time;
a second delay element coupled to the first delay element, the second delay element comprising a first constant delay time, wherein
the first constant delay time is chosen based on a delay caused during evaluation of control signals, and
the first constant delay time corresponds to a memory read command signal decoding delay time;
a phase comparator coupled to an output of the second delay element and to a clock input, wherein the phase comparator compares a phase of the clock input with a phase of a clock output of the second delay element; and
a control element coupled to the control signals, wherein the control element is operable to activate or deactivate the clock signal synchronizing device.
10. The clock signal synchronizing device according to claim 9 , wherein the clock signal synchronizing device provides a clock for a memory device.
11. The clock signal synchronizing device according to claim 10 , wherein the control signals comprise read control signals input to the memory device.
12. The clock signal synchronizing device according to claim 9 , further comprising a third delay element coupled between the second delay element and the phase comparator, the third delay element comprising a second constant delay time.
13. The clock signal synchronizing device according to claim 12 , wherein the second constant delay dyne is chosen based on signal delays caused by a receiver and/or an off-chip driver.
14. The clock signal synchronizing device according to claim 9 , further comprising:
a first signal output coupled to a clock output of the first delay element;
a second signal output coupled to the clock output oldie second delay element; and
a synchronized signal generator, the synchronized signal generator comprising a synchronized signal output derived from the clock output of the first delay element and the clock output of the second delay element.
15. The clock signal synchronizing device according to claim 14 , wherein the synchronized signal generator further comprises:
a first latch device clocked by the clock output of the second delay element; and
a second latch device clocked by the clock output of the first delay element wherein an output of the second latch device is coupled to an input of the first latch device, and wherein an output of the first latch device forms the synchronized signal output.
16. The clock signal synchronizing device according to claim 15 , wherein an input of the second latch device comprises a signal activated by an external read command signal.
17. A mobile phone or laptop comprising the clock signal synchronizing device according to claim 9 .
18. A method of using the clock signal synchronizing device according to claim 9 , the method comprising outputting a delayed clock signal if a corresponding read control signal is asserted at an input of the clock signal synchronizing device.
19. The method of using the clock signal synchronizing device according to claim 18 , wherein the first constant delay time corresponds to a memory read command signal decoding delay time.
20. A circuit comprising:
a variable delay element coupled to a clock input;
a first constant delay element coupled to an output of the variable delay element, the first constant delay clement comprising a delay time based on a decoding time of a read control signal;
a second constant delay element coupled to an output of the first constant delay element, the second constant delay element comprising a delay time based on a clock tree propagation time;
a phase comparator comprising
a first phase comparison input coupled to the clock input,
a second phase comparison input coupled to an output of the second constant delay element
a phase comparison output coupled to a delay control input of the variable delay element; and
an activation control circuit coupled to an enabling input of the variable delay element.
21. The circuit of claim 20 further comprising a system clock output coupled to the output of the variable delay element.
22. The circuit of claim 20 further comprising a system clock output coupled to the output of the first delay element.
23. A clock signal synchronizing device comprising:
a first delay element coupled to a clock input, the first delay element comprising a controllable variable delay time;
a second delay element coupled to the first delay element, the second delay element comprising a first constant delay time, wherein
the first constant delay time is chosen based on a delay caused during evaluation of control signals;
a phase comparator coupled to an output of the second delay element and to a clock input, wherein the phase comparator compares a phase of the clock input with a phase of a clock output of the second delay element;
a control element coupled to the control signals, wherein the control clement is operable to activate or deactivate the clock signal synchronizing device;
a first signal output coupled to a clock output of the first delay element;
a second signal output coupled to the clock output of the second delay element; and
a synchronized signal generator, the synchronized signal generator comprising
synchronized signal output derived from the clock output of the first delay element and the clock output of the second delay element,
a first latch device clocked by the clock output of the second delay element, and
a second latch device clocked by the clock output of the first delay element, wherein an output of the second latch device is coupled to an input of the first latch device, and wherein an output of the first latch device forms the synchronized signal output.